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1. 发明授权

US4344154A Programming sequence for electrically programmable memory 失效
标题翻译：电可编程存储器的编程顺序
公开(公告)号：US4344154A
公开(公告)日：1982-08-10
申请号：US118288
申请日：1980-02-04
申请人： Jeffrey M. Klaas , Paul A. Reed , Isam Rimawi
发明人： Jeffrey M. Klaas , Paul A. Reed , Isam Rimawi
IPC分类号： G11C16/08 , G11C16/10 , H03M7/00 , G11C7/02
CPC分类号： G11C16/10 , G11C16/08 , H03M7/005
摘要： An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. In a programming mode of operation, the application of high voltages to the row and column lines is controlled to prevent programming voltage from reaching a selected column until after all transistors in a row are turned on by programming voltage on a row line. This prevents unwanted programming conditions.
摘要翻译：具有浮动栅型存储单元的行和列的电可编程存储器阵列在单元列之间采用交替输出线和接地线，从而提供虚拟接地布置。一行由地址输入的一部分选择，另一部分选择一列。所选列的一侧的输出线被激活，另一侧的接地线。差分读出放大器响应所选输出线上的电压和参考电压。在编程操作模式下，对行和列线施加高电压进行控制，以防止编程电压到达所选择的列，直到在行中的所有晶体管通过编程在行线上的电压被接通。这可以防止不必要的编程条件。

2. 发明授权

US4387447A Column and ground select sequence in electrically programmable memory 失效
标题翻译：电可编程存储器中的列和地选序列
公开(公告)号：US4387447A
公开(公告)日：1983-06-07
申请号：US118349
申请日：1980-02-04
申请人： Jeffrey M. Klaas , Paul A. Reed , Isam Rimawi
发明人： Jeffrey M. Klaas , Paul A. Reed , Isam Rimawi
IPC分类号： G11C16/08 , G11C16/10 , H03M7/22 , G11C11/40 , G11C7/00
CPC分类号： G11C16/08 , G11C16/10 , H03M7/22
摘要： An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. To speed up the access time of the memory, the ground select is implemented and applied first, then the output of the ground select is used to generate the column select. In this manner, the biasing sequence for the array can begin before the decode of the column select has been completed.
摘要翻译：具有浮动栅型存储单元的行和列的电可编程存储器阵列在单元列之间采用交替输出线和接地线，从而提供虚拟接地布置。一行由地址输入的一部分选择，另一部分选择一列。所选列的一侧的输出线被激活，另一侧的接地线。差分读出放大器响应所选输出线上的电压和参考电压。为了加快存储器的访问时间，首先实现并应用接地选择，然后使用地选择的输出来生成列选择。以这种方式，阵列的偏置顺序可以在列选择的解码完成之前开始。

3. 发明授权

US4314362A Power down sequence for electrically programmable memory 失效
标题翻译：电可编程存储器的掉电序列
公开(公告)号：US4314362A
公开(公告)日：1982-02-02
申请号：US118287
申请日：1980-02-04
申请人： Jeffrey M. Klaas , Paul A. Reed , Isam Rimawi
发明人： Jeffrey M. Klaas , Paul A. Reed , Isam Rimawi
IPC分类号： G11C16/08 , G11C16/10 , H03M7/22 , G11C7/00
CPC分类号： H03M7/22 , G11C16/08 , G11C16/10
摘要： An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. A power down mode of operation is provided in which current flow in various circuits of the device is greatly reduced. To speed up access time in exiting from power down, the reference voltage input to the sense amplifier is shifted during power down then when exiting returns to its operating value according to a time constant.
摘要翻译：具有浮动栅型存储单元的行和列的电可编程存储器阵列在单元列之间采用交替输出线和接地线，从而提供虚拟接地布置。一行由地址输入的一部分选择，另一部分选择一列。所选列的一侧的输出线被激活，另一侧的接地线。差分读出放大器响应所选输出线上的电压和参考电压。提供了一种断电操作模式，其中大大减少了器件的各种电路中的电流。为了加快从掉电中退出的访问时间，输入到读出放大器的参考电压在掉电期间被移位，然后当退出时根据时间常数返回到其工作值。

4. 发明授权

US4818900A Predecode and multiplex in addressing electrically programmable memory 失效
标题翻译：寻址电可编程存储器中的预编码和多路复用
公开(公告)号：US4818900A
公开(公告)日：1989-04-04
申请号：US383637
申请日：1982-06-01
申请人： Jeffrey M. Klass , Paul A. Reed , Isam Rimawi
发明人： Jeffrey M. Klass , Paul A. Reed , Isam Rimawi
IPC分类号： G11C16/08 , G11C16/10 , H03M7/22 , H03K17/687
CPC分类号： G11C16/10 , G11C16/08 , H03M7/22
摘要： An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. The number of transistors needed in the decoder for the row select function is greatly reduced by employing predecoders which perform a 1-of-4 select for each pair of address bits, then using one of these select outputs to activate N multiplexers, and all the others as inputs to a decoder with N outputs to the multiplexers.
摘要翻译：具有浮动栅型存储单元的行和列的电可编程存储器阵列在单元列之间采用交替输出线和接地线，从而提供虚拟接地布置。一行由地址输入的一部分选择，另一部分选择一列。所选列的一侧的输出线被激活，另一侧的接地线。差分读出放大器响应所选输出线上的电压和参考电压。用于行选择功能的解码器中所需的晶体管数量通过采用为每对地址位执行1对4选择的预解码器而大大减少，然后使用这些选择输出中的一个激活N个多路复用器，并且所有其他作为输入到具有N个输出到多路复用器的解码器的输入。

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