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1. 发明授权

US6105083A Apparatus and method for controlling transfer of data between and processing of data by interconnected data processing elements 失效
标题翻译：用于通过互连的数据处理元件来控制数据传输和数据处理之间的装置和方法
公开(公告)号：US6105083A
公开(公告)日：2000-08-15
申请号：US879981
申请日：1997-06-20
申请人： Jeffrey D. Kurtze , Craig R. Frink , James Hamilton , Frank C. Sarnowski , Raymond D. Cacciatore , Scott A. Markinson , Michael F. Lamenza , Anthony O'Connor , Hamed Eshraghian
发明人： Jeffrey D. Kurtze , Craig R. Frink , James Hamilton , Frank C. Sarnowski , Raymond D. Cacciatore , Scott A. Markinson , Michael F. Lamenza , Anthony O'Connor , Hamed Eshraghian
IPC分类号： G06F13/38 , G06F13/42 , H04N7/24 , H04N7/26 , H04N7/50
CPC分类号： G06F13/4213 , H04N19/42 , H04N19/61 , H04N7/24
摘要： The present invention provides a generic interface which enables asynchronous data processing elements to be interconnected using an interconnection protocol that controls flow of data between the processing elements. The flow control allows the processing elements to be data independent from, i.e., the processing elements need not be designed for a fixed sample rate or resolution, sample format and other data dependent factors. When used with digital motion video data, the processing elements may process motion video data at various temporal and spatial resolutions and color formats. Flow of data between processing elements may be controlled by handshake signals indicating whether the sender has valid data and the receiver can receive data. When valid data is available at the sender and is requested by the receiver, a transfer of data occurs. The characteristics of the data, and functions to be performed on the data may be specified using control inputs to the processing elements. A counting circuit may be used to specify the number of the data samples for which the control inputs are valid. The interface allows each processing element to have a small number of storage locations for storing data, such as a pair of registers, which eliminates the need for large buffers and simplifies implementation of the processing element with such flow control as a simple integrated circuit.
摘要翻译：本发明提供了一种通用接口，其使得能够使用控制处理元件之间的数据流的互连协议来互连异步数据处理元件。流量控制允许处理元件与数据无关，即处理元件不需要被设计用于固定的采样率或分辨率，采样格式和其他依赖于数据的因素。当与数字运动视频数据一起使用时，处理元件可以处理各种时间和空间分辨率和颜色格式的运动视频数据。处理元件之间的数据流可以由指示发送者是否具有有效数据并且接收方可以接收数据的握手信号来控制。当有效数据在发送器处可用并且被接收器请求时，发生数据传送。可以使用对处理元件的控制输入来指定数据的特性和对数据执行的功能。可以使用计数电路来指定控制输入有效的数据样本的数量。该接口允许每个处理元件具有用于存储数据的少量存储位置，诸如一对寄存器，其消除了对大缓冲器的需要并且简化了具有如简单集成电路的流量控制的处理元件的实现。

2. 发明授权

US5446860A Apparatus for determining a computer memory configuration of memory modules using presence detect bits shifted serially into a configuration register 失效
标题翻译：用于使用连续移位到配置寄存器中的存在检测位来确定存储器模块的计算机存储器配置的装置
公开(公告)号：US5446860A
公开(公告)日：1995-08-29
申请号：US3194
申请日：1993-01-11
申请人： Scott A. Dresser , Scott A. Markinson , Richard B. Goud
发明人： Scott A. Dresser , Scott A. Markinson , Richard B. Goud
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00
CPC分类号： G06F12/0684
摘要： An apparatus is provided for determining a configuration of memory modules. Each of the memory modules produces presence detect bits. In a first feature, the apparatus includes an external register for receiving the presence detect bits from the memory modules in parallel and a memory controller integrated circuit. The memory controller integrated circuit includes an internal register for storing the presence detect bits and logic circuitry for determining a memory configuration. The presence detect bits are serially transferred from the external register to the internal register. In a second feature, the logic circuitry for determining a memory configuration includes comparator circuitry for comparing the presence detect bits of each pair of memory modules and generating a match signal or a mismatch signal. When a match signal occurs, the presence detect bits of the memory module pair are loaded into a memory configuration register. When a mismatch signal occurs, a mismatch code is loaded into the memory configuration register.
摘要翻译：提供了一种用于确定存储器模块的配置的装置。每个存储器模块产生存在检测位。在第一特征中，该装置包括用于从存储器模块并行地接收存在检测位的外部寄存器和存储器控制器集成电路。存储器控制器集成电路包括用于存储存在检测位的内部寄存器和用于确定存储器配置的逻辑电路。存在检测位从外部寄存器串行传输到内部寄存器。在第二特征中，用于确定存储器配置的逻辑电路包括用于比较每对存储器模块的存在检测位并产生匹配信号或失配信号的比较器电路。当匹配信号发生时，存储器模块对的存在检测位被加载到存储器配置寄存器中。当发生不匹配信号时，不匹配代码被加载到存储器配置寄存器中。

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