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1. 发明授权

US5446860A Apparatus for determining a computer memory configuration of memory modules using presence detect bits shifted serially into a configuration register 失效
标题翻译：用于使用连续移位到配置寄存器中的存在检测位来确定存储器模块的计算机存储器配置的装置
公开(公告)号：US5446860A
公开(公告)日：1995-08-29
申请号：US3194
申请日：1993-01-11
申请人： Scott A. Dresser , Scott A. Markinson , Richard B. Goud
发明人： Scott A. Dresser , Scott A. Markinson , Richard B. Goud
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00
CPC分类号： G06F12/0684
摘要： An apparatus is provided for determining a configuration of memory modules. Each of the memory modules produces presence detect bits. In a first feature, the apparatus includes an external register for receiving the presence detect bits from the memory modules in parallel and a memory controller integrated circuit. The memory controller integrated circuit includes an internal register for storing the presence detect bits and logic circuitry for determining a memory configuration. The presence detect bits are serially transferred from the external register to the internal register. In a second feature, the logic circuitry for determining a memory configuration includes comparator circuitry for comparing the presence detect bits of each pair of memory modules and generating a match signal or a mismatch signal. When a match signal occurs, the presence detect bits of the memory module pair are loaded into a memory configuration register. When a mismatch signal occurs, a mismatch code is loaded into the memory configuration register.
摘要翻译：提供了一种用于确定存储器模块的配置的装置。每个存储器模块产生存在检测位。在第一特征中，该装置包括用于从存储器模块并行地接收存在检测位的外部寄存器和存储器控制器集成电路。存储器控制器集成电路包括用于存储存在检测位的内部寄存器和用于确定存储器配置的逻辑电路。存在检测位从外部寄存器串行传输到内部寄存器。在第二特征中，用于确定存储器配置的逻辑电路包括用于比较每对存储器模块的存在检测位并产生匹配信号或失配信号的比较器电路。当匹配信号发生时，存储器模块对的存在检测位被加载到存储器配置寄存器中。当发生不匹配信号时，不匹配代码被加载到存储器配置寄存器中。

2. 发明授权

US4841434A Control sequencer with dual microprogram counters for microdiagnostics 失效
标题翻译：用于微诊断的双微程序计数器的控制定序器
公开(公告)号：US4841434A
公开(公告)日：1989-06-20
申请号：US42560
申请日：1987-04-27
申请人： James K. Mathewes, Jr. , Jan S. Hermam , Stephen C. Johnson , Richard B. Goud , Jack J. Stiffler
发明人： James K. Mathewes, Jr. , Jan S. Hermam , Stephen C. Johnson , Richard B. Goud , Jack J. Stiffler
IPC分类号： G06F9/28 , G06F11/22
CPC分类号： G06F11/22 , G06F9/28
摘要： A microprogrammed control unit of an information processing system having a control sequencer with dual microprogram counters for performing microdiagnostics simultaneously with performing macroprograms. The microdiagnostics comprise background and operability tests, the background tests being interleaved with macroinstruction operations under the control of the two independent microprogam counters. The background tests are run during processor idle time and the operability tests are executed at processor turn-on. The organization of the microdiagnostics into a hierarchical structure allows the use of the same microprogrammed test module for both the background and operability microdiagnostic tests. A prediction/residual coding technique provides fault detection for address and data information within the control sequencer.
摘要翻译：一种信息处理系统的微程序控制单元，具有具有双微程序计数器的控制定序器，用于与执行宏程序同时执行微诊断。微诊断包括背景和可操作性测试，背景测试与两个独立微焦点计数器控制下的宏指令操作交错。后台测试在处理器空闲时间运行，可操作性测试在处理器开启时执行。将微诊断组织成层次结构允许使用相同的微程序测试模块进行背景和可操作性微诊断测试。预测/残差编码技术为控制定序器内的地址和数据信息提供故障检测。

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