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1. 发明授权

US06686915B2 Systems and methods for rendering visual effects that are a function of depth 失效
标题翻译：用于渲染作为深度函数的视觉效果的系统和方法
公开(公告)号：US06686915B2
公开(公告)日：2004-02-03
申请号：US09838624
申请日：2001-04-19
申请人： Jeffrey A. Andrews
发明人： Jeffrey A. Andrews
IPC分类号： G06T1540
CPC分类号： G06T15/503
摘要： Systems and methods for accurately and realistically rendering a visual effect such as fog, colored liquids, gels, smoke, mists, and the like for which the visual appearance of the effect can change with respect to depth and for which the effect is rendered on a output display so as to be generally contained. Depth values are identified and passed to a visibility function in order to yield corresponding visibility values. An adjusted visibility function blends the obtained visibility values and yields an adjusted visibility value. This process for obtaining an adjusted visibility value is performed for every pixel of a display screen that is used to render the visual effect in order to accurately render the visual effect as it would be perceived in the real world.
摘要翻译：用于准确和实际地呈现视觉效果的系统和方法，例如雾，彩色液体，凝胶，烟雾，雾等，效果的视觉外观可以相对于深度而变化并且对其产生影响输出显示，以便被普遍包含。识别深度值并将其传递给可见性函数，以产生相应的可见性值。调整的可见度功能将获得的可见性值混合并产生调整的可见性值。对于用于呈现视觉效果的显示屏幕的每个像素执行用于获得调整的可视性值的该过程，以便准确地呈现在现实世界中将被感知的视觉效果。

2. 发明授权

US07650539B2 Observing debug counter values during system operation 失效
标题翻译：在系统运行期间观察调试计数器值
公开(公告)号：US07650539B2
公开(公告)日：2010-01-19
申请号：US11170818
申请日：2005-06-30
申请人： Susan E. Carrie , Jeffrey A. Andrews
发明人： Susan E. Carrie , Jeffrey A. Andrews
IPC分类号： G06F11/00
CPC分类号： G06F11/3648
摘要： A debugging architecture includes a set of debug counters for counting one or more events based on a set of signals from a device being monitored. The architecture provides for observing the outputs of the debug counters during operation of the device. The outputs of the counters are provided to an output bus (e.g., a Debug Bus) via an output bus interface during operation of the device being monitored. A data gathering system can access the output bus in order to gather the data from the counters for analysis.
摘要翻译：调试架构包括一组调试计数器，用于根据来自被监视设备的一组信号对一个或多个事件进行计数。该架构提供了在设备运行期间观察调试计数器的输出。在被监视的设备的操作期间，计数器的输出经由输出总线接口被提供给输出总线（例如，调试总线）。数据采集系统可以访问输出总线，以便从计数器收集数据进行分析。

3. 发明授权

US07095419B2 Applying multiple texture maps to objects in three-dimensional imaging processes 有权
标题翻译：在三维成像过程中应用多个纹理贴图到对象
公开(公告)号：US07095419B2
公开(公告)日：2006-08-22
申请号：US11216251
申请日：2005-08-31
申请人： Nicholas R. Baker , Jeffrey A. Andrews , Mei-Chi M. Liu
发明人： Nicholas R. Baker , Jeffrey A. Andrews , Mei-Chi M. Liu
IPC分类号： G09G5/00
CPC分类号： G06T15/04
摘要： Systems and methods for providing multi-pass rendering of three-dimensional objects. A rendering pipeline that includes (N) physical texture units and one or more associated buffers emulates a rendering pipeline containing more texture units (M) than are physically present (N). Multiple rendering passes are performed for each pixel. During each texture pass only N sets of texture coordinates are passed to the texture units. The number of passes required through the pipeline to emulate M texture units is M/N, rounded up to the next integer. The N texture units of the rendering pipeline perform look-ups on a given pass for the corresponding N texture maps. The texture values obtained during the texture passes are blended by texture blenders to provide composite texture values. In successive passes, the buffers are used for temporary data and the most current composite texture values. The process is repeated until all desired texture maps are applied.
摘要翻译：用于提供三维物体的多遍渲染的系统和方法。包括（N）个物理结构单元和一个或多个相关联的缓冲器的渲染管线模拟包含比物理存在（N）更多的纹理单位（M）的渲染管线。对每个像素执行多个渲染遍。在每个纹理过程中，只有N组纹理坐标传递给纹理单元。通过流水线模拟M个纹理单元所需的通过次数为M / N，舍入到下一个整数。渲染流水线的N个纹理单元在相应的N个纹理贴图的给定遍历上执行查找。在纹理过程中获得的纹理值由纹理混合器混合以提供复合纹理值。在连续遍中，缓冲区用于临时数据和最新的复合纹理值。重复该过程，直到应用所有期望的纹理图。

4. 发明授权

US06741259B2 Applying multiple texture maps to objects in three-dimensional imaging processes 有权
标题翻译：在三维成像过程中应用多个纹理贴图到对象
公开(公告)号：US06741259B2
公开(公告)日：2004-05-25
申请号：US09939130
申请日：2001-08-24
申请人： Nicholas R. Baker , Jeffrey A. Andrews , Mei-Chi M. Liu
发明人： Nicholas R. Baker , Jeffrey A. Andrews , Mei-Chi M. Liu
IPC分类号： G09G500
CPC分类号： G06T15/04
摘要： Systems and methods for providing multi-pass rendering of three-dimensional objects. A rendering pipeline is used that includes one or more (N) physical texture units and one or more associated frame buffers to emulate a rendering pipeline containing more texture units (M) than are actually physically present (N). Multiple rendering passes are performed for each pixel of a frame. During each texture pass for each pixel of a frame, only N sets of texture coordinates are passed to the texture units. The number of passes required through the pipeline to emulate M texture units is M/N, rounded up to the next integer number of passes. The N texture units of the rendering pipeline perform the look-ups on a given pass for the correspondingly bound N texture maps. The texture values obtained during the texture passes for each pixel are blended by complementary texture blenders to provide composite texture values for each of the pixels of the frame. In successive passes, the frame buffers are used to support any necessary extra temporary data and to store the most current composite texture values for all of the pixels of the frame. The process is repeated until all desired texture maps are applied in order to render the desired three-dimensional object.
摘要翻译：用于提供三维物体的多遍渲染的系统和方法。使用包括一个或多个（N）个物理纹理单元和一个或多个相关联的帧缓冲器的渲染管线来模拟包含比实际存在的（N）更多的纹理单位（M）的渲染管线。对帧的每个像素执行多个渲染遍。在帧的每个像素的每个纹理通过期间，只有N组纹理坐标被传递到纹理单元。通过管道模拟M个纹理单元所需的通过次数为M / N，向上取整到下一个整数。渲染流水线的N个纹理单元对相应的N个纹理贴图给定的遍历执行查找。通过互补纹理混合器混合在每个像素的纹理通过期间获得的纹理值，以为帧的每个像素提供复合纹理值。在连续的遍历中，帧缓冲器用于支持任何必要的额外的临时数据并存储帧的所有像素的最新的复合纹理值。重复该过程，直到应用所有期望的纹理图以呈现所需的三维物体。

5. 发明授权

US07653802B2 System and method for using address lines to control memory usage 有权
标题翻译：使用地址线控制内存使用的系统和方法
公开(公告)号：US07653802B2
公开(公告)日：2010-01-26
申请号：US10928786
申请日：2004-08-27
申请人： Dinarte R. Morais , Jeffrey A. Andrews
发明人： Dinarte R. Morais , Jeffrey A. Andrews
IPC分类号： G06F9/32
CPC分类号： G06F12/10 , G06F12/1027 , G06F12/145
摘要： A computing environment maintains the integrity of data stored in system memory. The system has a memory management unit that maintains a plurality of real page numbers. The system also comprises an address bus in communication with the memory management unit. The address bus comprises a plurality of address lines, wherein a value of at least one address line is set by a real page number from the memory management unit. The system has an operating system that controls memory usage by controlling the real page numbers stored in said page table that is accessed by the memory management unit. At least one security feature such as data encryption is selectively applied to data stored in a page of said memory as enabled by a value of said address line set by said real page number.
摘要翻译：计算环境维护存储在系统存储器中的数据的完整性。该系统具有维持多个真实页码的存储器管理单元。该系统还包括与存储器管理单元通信的地址总线。地址总线包括多个地址线，其中至少一个地址线的值由来自存储器管理单元的实际页号设置。该系统具有通过控制由存储器管理单元访问的存储在所述页表中的真实页码来控制存储器使用的操作系统。至少一个诸如数据加密的安全特征被选择性地应用于由所述真实页码设置的所述地址线的值所启用的存储在所述存储器的页面中的数据。

6. 发明授权

US07444523B2 System and method for using address bits to signal security attributes of data in the address space 有权
标题翻译：使用地址位来表示地址空间中数据的安全属性的系统和方法
公开(公告)号：US07444523B2
公开(公告)日：2008-10-28
申请号：US10928970
申请日：2004-08-27
申请人： Dinarte R. Morais , Jeffrey A. Andrews
发明人： Dinarte R. Morais , Jeffrey A. Andrews
IPC分类号： H04L9/32 , H04L9/00
CPC分类号： G06F21/85 , G06F21/78
摘要： A integrity control system uses the address bits to enable encryption and/or protection of data stored in a system memory. The encryption and protection mechanisms are coupled to the CPU by way of a data bus and to the memory by way of a data bus. An address bus that determines the location of data to be stored or retrieved from system memory has a plurality of address lines. At least one of the address lines enabling the encryption mechanism to encrypt data before storage in the memory and to decrypt data after retrieval from memory. Another address line enables the protection mechanism to generate a hash of the data. The hash is stored and used to determine whether data has been altered while stored in system memory.
摘要翻译：完整性控制系统使用地址位来启用对存储在系统存储器中的数据的加密和/或保护。加密和保护机制通过数据总线和数据总线连接到CPU。确定要从系统存储器存储或检索的数据的位置的地址总线具有多个地址线。至少一个地址线使加密机制能够在存储器中存储之前对数据进行加密，并且在从存储器检索之后解密数据。另一个地址线使得保护机制能够生成数据的散列。哈希存储并用于确定在存储在系统内存中数据是否已更改。

7. 发明授权

US06975327B2 Applying multiple texture maps to objects in three-dimensional imaging processes 失效
标题翻译：在三维成像过程中应用多个纹理贴图到对象
公开(公告)号：US06975327B2
公开(公告)日：2005-12-13
申请号：US10770054
申请日：2004-02-02
申请人： Nicholas R. Baker , Jeffrey A. Andrews , Mei-Chi M. Liu
发明人： Nicholas R. Baker , Jeffrey A. Andrews , Mei-Chi M. Liu
IPC分类号： G06T15/20 , G09G5/00
CPC分类号： G06T15/04
摘要： Systems and methods for providing multi-pass rendering of three-dimensional objects. A rendering pipeline that includes (N) physical texture units and one or more associated buffers emulates a rendering pipeline containing more texture units (M) than are physically present (N). Multiple rendering passes are performed for each pixel. During each texture pass only N sets of texture coordinates are passed to the texture units. The number of passes required through the pipeline to emulate M texture units is M/N, rounded up to the next integer. The N texture units of the rendering pipeline perform look-ups on a given pass for the corresponding N texture maps. The texture values obtained during the texture passes are blended by texture blenders to provide composite texture values. In successive passes, the buffers are used for temporary data and the most current composite texture values. The process is repeated until all desired texture maps are applied.
摘要翻译：用于提供三维物体的多遍渲染的系统和方法。包括（N）个物理结构单元和一个或多个相关联的缓冲器的渲染管线模拟包含比物理存在（N）更多的纹理单位（M）的渲染管线。对每个像素执行多个渲染遍。在每个纹理过程中，只有N组纹理坐标传递给纹理单元。通过流水线模拟M个纹理单元所需的通过次数为M / N，舍入到下一个整数。渲染流水线的N个纹理单元在相应的N个纹理贴图的给定遍历上执行查找。在纹理过程中获得的纹理值由纹理混合器混合以提供复合纹理值。在连续遍中，缓冲区用于临时数据和最新的复合纹理值。重复该过程，直到应用所有期望的纹理图。

8. 发明授权

US06862027B2 System and method for parallel execution of data generation tasks 失效
标题翻译：并行执行数据生成任务的系统和方法
公开(公告)号：US06862027B2
公开(公告)日：2005-03-01
申请号：US10611415
申请日：2003-06-30
申请人： Jeffrey A. Andrews , Nicholas R. Baker , J. Andrew Goossen , Michael Abrash
发明人： Jeffrey A. Andrews , Nicholas R. Baker , J. Andrew Goossen , Michael Abrash
IPC分类号： G06F12/08 , G06F9/46 , G06F9/50 , G06F13/28 , G06F15/16 , G06F15/78 , G06F15/80 , G06T1/60 , G06T15/00 , G09G5/36
CPC分类号： G06F15/7846
摘要： A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory. The GPU retrieves the output data from the locked set, and periodically forwards a tail pointer to a cacheable location within the data-generating elements that informs the data-generating elements of its progress in retrieving the output data.
摘要翻译： CPU模块包括被配置为执行高级主机相关任务的主机元件，以及被配置为执行与高级主机相关任务相关联的数据生成任务的一个或多个数据生成处理元件。每个数据生成处理元件包括被配置为接收输入数据的逻辑和被配置为处理输入数据以产生输出数据的逻辑。输出数据量大于输入数据量，并且输入数据量与输出数据量的比率定义了解压比。在一个实现中，由主机元件执行的与主机相关的高级别任务涉及高级图形处理任务，并且数据生成任务涉及生成几何数据（例如三角形顶点），用于在高级图形处理任务。 CPU模块可以经由至少一个锁定的高速缓存存储器将输出数据传送到GPU模块。 GPU从锁定的集合中检索输出数据，并周期性地将尾部指针转发到数据生成元素内的可缓存位置，以向数据生成元素通知其在检索输出数据时的进度。

9. 发明授权

US07822993B2 System and method for using address bits to affect encryption 有权
标题翻译：使用地址位影响加密的系统和方法
公开(公告)号：US07822993B2
公开(公告)日：2010-10-26
申请号：US10927729
申请日：2004-08-27
申请人： Dinarte R. Morais , Jeffrey A. Andrews , William E. Hall
发明人： Dinarte R. Morais , Jeffrey A. Andrews , William E. Hall
IPC分类号： G06F11/30
CPC分类号： G06F12/1408 , G06F12/1475
摘要： A computing environment maintains the confidentiality of data stored in system memory. The computing environment has an encryption circuit in communication with a CPU. The system memory is also in communication with the encryption circuit. An address bus having a plurality of address lines forms part of the system and a value of at least one of the address lines determines a key selected from a plurality of keys to use in the encryption circuit to encrypt data being transferred by the CPU to the memory.
摘要翻译：计算环境维护存储在系统存储器中的数据的机密性。计算环境具有与CPU通信的加密电路。系统存储器也与加密电路通信。具有多个地址线的地址总线形成系统的一部分，并且至少一个地址线的值确定从多个密钥中选择的密钥以在加密电路中使用以将由CPU传送的数据加密到记忆。

10. 发明授权

US07356668B2 System and method for using address bits to form an index into secure memory 有权
标题翻译：使用地址位形成安全存储器的索引的系统和方法
公开(公告)号：US07356668B2
公开(公告)日：2008-04-08
申请号：US10928519
申请日：2004-08-27
申请人： Dinarte R. Morais , Jeffrey A. Andrews
发明人： Dinarte R. Morais , Jeffrey A. Andrews
IPC分类号： G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/1408 , G06F21/57
摘要： A integrity control system uses the address bits to enable protection of data stored in a system memory. An address bus that determines the location of data to be stored or retrieved from system memory has a plurality of address lines. A subset of the address lines enables the protection mechanism to generate an integrity control value representative of the data and determine where the integrity check value is stored in a secure memory.
摘要翻译：完整性控制系统使用地址位来保护存储在系统存储器中的数据。确定要从系统存储器存储或检索的数据的位置的地址总线具有多个地址线。地址线的子集使得保护机制能够生成表示数据的完整性控制值，并确定完整性校验值存储在安全存储器中的位置。

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