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1. 发明授权

US06862027B2 System and method for parallel execution of data generation tasks 失效
标题翻译：并行执行数据生成任务的系统和方法
公开(公告)号：US06862027B2
公开(公告)日：2005-03-01
申请号：US10611415
申请日：2003-06-30
申请人： Jeffrey A. Andrews , Nicholas R. Baker , J. Andrew Goossen , Michael Abrash
发明人： Jeffrey A. Andrews , Nicholas R. Baker , J. Andrew Goossen , Michael Abrash
IPC分类号： G06F12/08 , G06F9/46 , G06F9/50 , G06F13/28 , G06F15/16 , G06F15/78 , G06F15/80 , G06T1/60 , G06T15/00 , G09G5/36
CPC分类号： G06F15/7846
摘要： A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory. The GPU retrieves the output data from the locked set, and periodically forwards a tail pointer to a cacheable location within the data-generating elements that informs the data-generating elements of its progress in retrieving the output data.
摘要翻译： CPU模块包括被配置为执行高级主机相关任务的主机元件，以及被配置为执行与高级主机相关任务相关联的数据生成任务的一个或多个数据生成处理元件。每个数据生成处理元件包括被配置为接收输入数据的逻辑和被配置为处理输入数据以产生输出数据的逻辑。输出数据量大于输入数据量，并且输入数据量与输出数据量的比率定义了解压比。在一个实现中，由主机元件执行的与主机相关的高级别任务涉及高级图形处理任务，并且数据生成任务涉及生成几何数据（例如三角形顶点），用于在高级图形处理任务。 CPU模块可以经由至少一个锁定的高速缓存存储器将输出数据传送到GPU模块。 GPU从锁定的集合中检索输出数据，并周期性地将尾部指针转发到数据生成元素内的可缓存位置，以向数据生成元素通知其在检索输出数据时的进度。

2. 发明授权

US07333114B2 System and method for parallel execution of data generation tasks 失效
标题翻译：并行执行数据生成任务的系统和方法
公开(公告)号：US07333114B2
公开(公告)日：2008-02-19
申请号：US11027454
申请日：2004-12-30
申请人： Jeffrey A. Andrews , Nicholas R. Baker , J. Andrew Goossen , Michael Abrash
发明人： Jeffrey A. Andrews , Nicholas R. Baker , J. Andrew Goossen , Michael Abrash
IPC分类号： G06F15/16 , G06F12/00 , G09G5/36
CPC分类号： G06F15/7846
摘要： A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory. The GPU retrieves the output data from the locked set, and periodically forwards a tail pointer to a cacheable location within the data-generating elements that informs the data-generating elements of its progress in retrieving the output data.
摘要翻译： CPU模块包括被配置为执行高级主机相关任务的主机元件，以及被配置为执行与高级主机相关任务相关联的数据生成任务的一个或多个数据生成处理元件。每个数据生成处理元件包括被配置为接收输入数据的逻辑和被配置为处理输入数据以产生输出数据的逻辑。输出数据量大于输入数据量，并且输入数据量与输出数据量的比率定义了解压比。在一个实现中，由主机元件执行的与主机相关的高级别任务涉及高级图形处理任务，并且数据生成任务涉及生成几何数据（例如三角形顶点），用于在高级图形处理任务。 CPU模块可以经由至少一个锁定的高速缓存存储器将输出数据传送到GPU模块。 GPU从锁定的集合中检索输出数据，并周期地将尾部指针转发到数据生成元素内的可缓存位置，该数据生成元素通知数据生成元素在获取输出数据时的进度。

3. 发明申请

US20050122339A1 System and method for parallel execution of data generation tasks 失效
公开(公告)号：US20050122339A1
公开(公告)日：2005-06-09
申请号：US11027454
申请日：2004-12-30
申请人： Jeffrey Andrews , Nicholas Baker , J. Goossen , Michael Abrash
发明人： Jeffrey Andrews , Nicholas Baker , J. Goossen , Michael Abrash
IPC分类号： G06F12/08 , G06F9/46 , G06F9/50 , G06F13/28 , G06F15/16 , G06F15/78 , G06F15/80 , G06T1/60 , G06T15/00 , G09G5/36
CPC分类号： G06F15/7846
摘要： A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory. The GPU retrieves the output data from the locked set, and periodically forwards a tail pointer to a cacheable location within the data-generating elements that informs the data-generating elements of its progress in retrieving the output data.

4. 发明授权

US08892848B2 Processor and system using a mask register to track progress of gathering and prefetching elements from memory 有权
标题翻译：处理器和系统使用掩码寄存器跟踪从内存中采集和预取元素的进度
公开(公告)号：US08892848B2
公开(公告)日：2014-11-18
申请号：US13175953
申请日：2011-07-05
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
IPC分类号： G06F9/312 , G06F9/30 , G06F12/02 , G06F9/345 , G06F9/38 , G06F15/80
CPC分类号： G06F15/8069 , G06F9/30043 , G06F9/30047 , G06F9/30098 , G06F9/30101 , G06F9/345 , G06F9/383 , G06F12/02 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/6028
摘要： A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
摘要翻译：一种用于将值分配给第一寄存器中的元件的装置，系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段，值可以指示相应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中每个数据域的值，并且为第一寄存器中的每个数据字段具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。描述和要求保护其他实施例。

5. 发明申请

US20110264863A1 DEVICE, SYSTEM, AND METHOD FOR USING A MASK REGISTER TO TRACK PROGRESS OF GATHERING ELEMENTS FROM MEMORY 有权
标题翻译：使用掩码寄存器跟踪记忆元素进度的设备，系统和方法
公开(公告)号：US20110264863A1
公开(公告)日：2011-10-27
申请号：US13175953
申请日：2011-07-05
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
IPC分类号： G06F12/08 , G06F9/30
CPC分类号： G06F15/8069 , G06F9/30043 , G06F9/30047 , G06F9/30098 , G06F9/30101 , G06F9/345 , G06F9/383 , G06F12/02 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/6028
摘要： A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
摘要翻译：一种用于将值分配给第一寄存器中的元件的装置，系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段，值可以指示相应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中每个数据域的值，并且为第一寄存器中的每个数据字段具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。描述和要求保护其他实施例。

6. 发明申请

US20060095672A1 System and method for parallel execution of data generation tasks 审中-公开
标题翻译：并行执行数据生成任务的系统和方法
公开(公告)号：US20060095672A1
公开(公告)日：2006-05-04
申请号：US11065343
申请日：2005-02-25
申请人： Jeffrey Andrews , Nicholas Baker , J. Goossen , Michael Abrash , Russell Hoover , Eric Mejdrich , Sandra Woodward
发明人： Jeffrey Andrews , Nicholas Baker , J. Goossen , Michael Abrash , Russell Hoover , Eric Mejdrich , Sandra Woodward
IPC分类号： G06F12/14
CPC分类号： G06F15/7846
摘要： A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory. The GPU retrieves the output data from the locked set, and periodically forwards a tail pointer to a cacheable location within the data-generating elements that informs the data-generating elements of its progress in retrieving the output data
摘要翻译： CPU模块包括被配置为执行高级主机相关任务的主机元件，以及被配置为执行与高级主机相关任务相关联的数据生成任务的一个或多个数据生成处理元件。每个数据生成处理元件包括被配置为接收输入数据的逻辑和被配置为处理输入数据以产生输出数据的逻辑。输出数据量大于输入数据量，并且输入数据量与输出数据量的比率定义了解压比。在一个实现中，由主机元件执行的与主机相关的高级别任务涉及高级图形处理任务，并且数据生成任务涉及生成几何数据（例如三角形顶点），用于在高级图形处理任务。 CPU模块可以经由至少一个锁定的高速缓存存储器将输出数据传送到GPU模块。 GPU从锁定的集合中检索输出数据，并周期性地将尾部指针转发到数据生成元素内的可缓存位置，以向数据生成元素通知其在检索输出数据中的进度

7. 发明授权

US08681173B2 Device, system, and method for improving processing efficiency by collectively applying operations 有权
标题翻译：通过集体应用操作提高处理效率的装置，系统和方法
公开(公告)号：US08681173B2
公开(公告)日：2014-03-25
申请号：US11967492
申请日：2007-12-31
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
IPC分类号： G09G5/00
CPC分类号： G06T1/20 , G06F9/3867
摘要： A system and method for generating a single compressed vector including two or more predetermined attribute values. For each of a plurality of data points such as pixels, if a first and a second attribute values of the data point are equal to a first and a second, respectively, of the two or more predetermined attribute values, the compressed vector is used to operate on the data point. Other embodiments are described and claimed.
摘要翻译：一种用于生成包括两个或多个预定属性值的单个压缩向量的系统和方法。对于诸如像素的多个数据点中的每一个，如果数据点的第一和第二属性值分别等于两个或更多个预定属性值的第一和第二属性值，则使用压缩向量在数据点上操作。描述和要求保护其他实施例。

8. 发明授权

US5818465A Fast display of images having a small number of colors with a VGA-type adapter 失效
标题翻译：使用VGA型适配器快速显示具有少量颜色的图像
公开(公告)号：US5818465A
公开(公告)日：1998-10-06
申请号：US661812
申请日：1996-06-11
申请人： Michael Abrash
发明人： Michael Abrash
IPC分类号： G09G5/02 , G09G5/39 , G09G5/393 , G09G5/06
CPC分类号： G09G5/393 , G09G5/02
摘要： An approach to outputting 256-color pixel data more quickly than conventional systems is provided. In this approach, a word of data encoding a color bit map for up to eight pixels may be stored in a system buffer and then written to a video adapter. The video adapter is configured such that color codes for multiple pixels may be simultaneously written into the planes of the display memory of the adapter. As a result, 256-color pixel data may be more quickly drawn on a video display than in conventional systems.
摘要翻译：提供了一种比传统系统更快速地输出256色像素数据的方法。在这种方法中，将编码最多八个像素的彩色位图的数据字可以存储在系统缓冲器中，然后写入视频适配器。视频适配器被配置为使得可以将多个像素的颜色代码同时写入适配器的显示存储器的平面中。结果，在常规系统中，可以在视频显示器上更快速地绘制256色像素数据。

9. 发明授权

US07984273B2 System and method for using a mask register to track progress of gathering elements from memory 有权
标题翻译：使用掩码寄存器跟踪从内存中收集元素的进度的系统和方法
公开(公告)号：US07984273B2
公开(公告)日：2011-07-19
申请号：US11967482
申请日：2007-12-31
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
IPC分类号： G06F9/312
CPC分类号： G06F15/8069 , G06F9/30043 , G06F9/30047 , G06F9/30098 , G06F9/30101 , G06F9/345 , G06F9/383 , G06F12/02 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/6028
摘要： A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
摘要翻译：一种用于向第一寄存器中的元素分配值的系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段，第一值可以指示对应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中的每个数据字段的值，并且对于每个数据在第一寄存器中具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。描述和要求保护其他实施例。

10. 发明申请

US20090172364A1 DEVICE, SYSTEM, AND METHOD FOR GATHERING ELEMENTS FROM MEMORY 有权
标题翻译：用于从记忆中获取元素的装置，系统和方法
公开(公告)号：US20090172364A1
公开(公告)日：2009-07-02
申请号：US11967482
申请日：2007-12-31
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
IPC分类号： G06F9/315 , G06F12/02
CPC分类号： G06F15/8069 , G06F9/30043 , G06F9/30047 , G06F9/30098 , G06F9/30101 , G06F9/345 , G06F9/383 , G06F12/02 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/6028
摘要： A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
摘要翻译：一种用于向第一寄存器中的元素分配值的系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段，第一值可以指示对应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中的每个数据字段的值，并且对于每个数据在第一寄存器中具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。描述和要求保护其他实施例。

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