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1. 发明申请

US20130326459A1 POWER/PERFORMANCE OPTIMIZATION THROUGH TEMPERATURE/VOLTAGE CONTROL 有权
标题翻译：功率/性能优化通过温度/电压控制
公开(公告)号：US20130326459A1
公开(公告)日：2013-12-05
申请号：US13749851
申请日：2013-01-25
申请人： Jeanne P. Bickford , Eric A. Foreman , Mark W. Kuemerle , Susan K. Lichtensteiger
发明人： Jeanne P. Bickford , Eric A. Foreman , Mark W. Kuemerle , Susan K. Lichtensteiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31721 , G06F17/5031
摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.
摘要翻译：一种优化集成电路（IC）芯片的功率和定时的方法，识别允许根据集成电路芯片设计产生的集成电路芯片在平均功耗目标和时序延迟目标内工作的多个有效的温度和电压组合。这种方法从每个集成电路芯片的有效温度和电压组合中选择温度切割点，计算每个温度切断点的功率消耗量，并且基于功耗量调节温度切断点直到温度切点实现了平均功耗目标。接下来，该方法测试每个集成电路芯片，并将温度切割点记录在集成电路芯片的存储器中。

2. 发明授权

US08839170B2 Power/performance optimization through temperature/voltage control 有权
标题翻译：通过温度/电压控制实现功率/性能优化
公开(公告)号：US08839170B2
公开(公告)日：2014-09-16
申请号：US13749851
申请日：2013-01-25
申请人： Jeanne P. Bickford , Eric A. Foreman , Mark W. Kuemerle , Susan K. Lichtensteiger
发明人： Jeanne P. Bickford , Eric A. Foreman , Mark W. Kuemerle , Susan K. Lichtensteiger
IPC分类号： G06F17/50 , G01R31/317
CPC分类号： G06F17/5045 , G01R31/31721 , G06F17/5031
摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.
摘要翻译：一种优化集成电路（IC）芯片的功率和定时的方法，识别允许根据集成电路芯片设计产生的集成电路芯片在平均功耗目标和时序延迟目标内工作的多个有效的温度和电压组合。这种方法从每个集成电路芯片的有效温度和电压组合中选择温度切割点，计算每个温度切断点的功率消耗量，并且基于功耗量调节温度切断点直到温度切点实现了平均功耗目标。接下来，该方法测试每个集成电路芯片，并将温度切割点记录在集成电路芯片的存储器中。

3. 发明授权

US08543960B1 Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures 失效
标题翻译：通过各种温度范围内的电压修改对集成电路进行功率和时序优化
公开(公告)号：US08543960B1
公开(公告)日：2013-09-24
申请号：US13484451
申请日：2012-05-31
申请人： Jeanne P. Bickford , Eric A. Foreman , Mark W. Kuemerle , Susan K. Lichtensteiger
发明人： Jeanne P. Bickford , Eric A. Foreman , Mark W. Kuemerle , Susan K. Lichtensteiger
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/3004 , G01R31/3016 , G01R31/31725 , G06F17/5031
摘要： A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance.
摘要翻译：一种通过修改提供给IC芯片的电压同时满足较低和较高温度范围内的功率消耗和定时延迟性能来优化集成电路（IC）芯片的功率和定时的方法，该集成电路（IC）芯片使用显示温度反转的IC技术。选择高电压，以满足整个温度范围内的闭合时序分析，以满足定时性能，并选择低电压以满足更高温度下的温度下降温度范围内的定时性能和功率性能范围。 IC芯片在高电压下导通，并且当超过温度切断点时将高电压降低到低电压以满足功率性能同时保持定时性能。

4. 发明授权

US09152168B2 Systems and methods for system power estimation 有权
标题翻译：系统功率估计的系统和方法
公开(公告)号：US09152168B2
公开(公告)日：2015-10-06
申请号：US13605050
申请日：2012-09-06
申请人： Jeanne P. Bickford , Rebecca A. Bickford , Susan K. Lichtensteiger , Jeanne H. Raymond
发明人： Jeanne P. Bickford , Rebecca A. Bickford , Susan K. Lichtensteiger , Jeanne H. Raymond
IPC分类号： G06F17/50 , G06F1/00
CPC分类号： G06F1/00 , G06F1/32
摘要： Methods and systems for system power estimation are provided. A method implemented in a computer infrastructure includes separating products into different segments. The method also includes calculating a power estimation for each segment based on operating conditions of each respective segment. The method further includes calculating an average system power estimation. At least one of the separating, calculating the power estimation, and calculating the average system power estimation is performed using a processor.
摘要翻译：提供了系统功率估计的方法和系统。在计算机基础设施中实现的方法包括将产品分成不同的段。该方法还包括基于每个相应段的操作条件来计算每个段的功率估计。该方法还包括计算平均系统功率估计。使用处理器执行分离，计算功率估计和计算平均系统功率估计中的至少一个。

5. 发明申请

US20130113514A1 SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL 有权
标题翻译：用于动态和自适应功率控制的速度波动
公开(公告)号：US20130113514A1
公开(公告)日：2013-05-09
申请号：US13288269
申请日：2011-11-03
申请人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
发明人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
IPC分类号： H03K19/00 , G06F17/50
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译：由相同的电路设计制造多个数字电路。功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。数字电路分为不同的电压箱，每个电压箱都有漏电极限。已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。非易失性存储介质存储电压仓的边界作为速度分级测试数据。功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

6. 发明授权

US08421495B1 Speed binning for dynamic and adaptive power control 有权
标题翻译：用于动态和自适应功率控制的速度分组
公开(公告)号：US08421495B1
公开(公告)日：2013-04-16
申请号：US13288269
申请日：2011-11-03
申请人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
发明人： Theodoros E. Anemikos , Jeanne P. Bickford , Nazmul Habib , Susan K. Lichtensteiger
IPC分类号： H03K19/003
CPC分类号： H03K19/0013
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connect to the digital circuits, and a non-volatile storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-volatile storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译：由相同的电路设计制造多个数字电路。功率控制器可操作地连接到数字电路，并且非易失性存储介质可操作地连接到功率控制器。数字电路分为不同的电压箱，每个电压箱都有漏电极限。已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。非易失性存储介质存储电压仓的边界作为速度分级测试数据。功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

7. 发明授权

US09157956B2 Adaptive power control using timing canonicals 有权
标题翻译：使用定时规范的自适应功率控制
公开(公告)号：US09157956B2
公开(公告)日：2015-10-13
申请号：US13614564
申请日：2012-09-13
申请人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
发明人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
IPC分类号： G06F17/50 , G01R31/317 , G01R31/30
CPC分类号： G01R31/31718 , G01R31/3008
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译：由相同的电路设计制造多个数字电路。功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。数字电路分为不同的电压箱，每个电压箱都有漏电极限。已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。非瞬时存储介质存储电压仓的边界作为速度分组测试数据。功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

8. 发明申请

US20140074422A1 ADAPTIVE POWER CONTROL USING TIMING CANONICALS 有权
标题翻译：使用时代标准的自适应功率控制
公开(公告)号：US20140074422A1
公开(公告)日：2014-03-13
申请号：US13614564
申请日：2012-09-13
申请人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
发明人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
IPC分类号： G06F17/50 , G06F19/00 , G01R31/317
CPC分类号： G01R31/31718 , G01R31/3008
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译：由相同的电路设计制造多个数字电路。功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。数字电路分为不同的电压箱，每个电压箱都有漏电极限。已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。非瞬时存储介质存储电压仓的边界作为速度分组测试数据。功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

9. 发明授权

US09557378B2 Method and structure for multi-core chip product test and selective voltage binning disposition 有权
标题翻译：多核芯片产品测试和选择性电压组合配置的方法和结构
公开(公告)号：US09557378B2
公开(公告)日：2017-01-31
申请号：US13553986
申请日：2012-07-20
申请人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
发明人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
IPC分类号： H01L21/66 , G01R31/02 , G06F19/00 , G01R31/317 , G06F1/32
CPC分类号： G01R31/31718 , G01R31/31725 , G06F1/32
摘要： Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.
摘要翻译：测试集成电路器件的工作速度，以在最大和最小电压下建立最大和最小频率。将器件分类为相对较慢且相对较快的器件，以将器件分类到不同的电压仓。对于在系统使用条件下核心性能所需的每个电压箱，建立了一个特定于特定电压限制。特定于箱体的电压限制与系统最大和最小频率规格下的核心最小芯片级功能电压进行比较。该方法在设计最大和最小电压条件下将设计最大和最小频率的系统设计评估与测试的最大和最小电压条件下的最大和最小频率进行了评估。为器件建立芯片专用功能电压限制。来自电压仓的所有器件的初始系统电压设置在特定于器件的电压限制和芯片专用功能电压限制的更大值与评估条件一致。

10. 发明授权

US09429619B2 Reliability test screen optimization 有权
标题翻译：可靠性测试屏幕优化
公开(公告)号：US09429619B2
公开(公告)日：2016-08-30
申请号：US13564337
申请日：2012-08-01
申请人： Theodoros E. Anemikos , Jeanne P. Bickford , Douglas S. Dewey , Ernest A. Viau, Jr.
发明人： Theodoros E. Anemikos , Jeanne P. Bickford , Douglas S. Dewey , Ernest A. Viau, Jr.
IPC分类号： G06F19/00 , G01R31/28 , G05B19/418 , G01R31/317
CPC分类号： G01R31/2894 , G01R31/2855 , G01R31/2868 , G01R31/287 , G01R31/2879 , G01R31/31718 , G05B19/41875 , Y02P90/14 , Y02P90/265
摘要： Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.
摘要翻译：方法和系统通过将制造后的集成电路器件分类为相对较慢的集成电路器件和相对较快的集成电路器件来将集成电路器件分类到不同的电压仓中来优化集成电路设计中的功率利用。方法和系统为每个电压仓建立一个二进制特定的可靠性测试过程，并使用测试仪测试集成电路器件。这允许方法和系统将不合格的集成电路设备中的缺陷识别为相应电压箱的专用集成电路可靠性测试过程。所述方法和系统移除集成电路器件中的有缺陷的集成电路器件，以便只允许无故障的集成电路器件保持并向客户提供无缺陷的集成电路器件。

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