专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06678875B2 Self-contained embedded test design environment and environment setup utility 失效
标题翻译：独立的嵌入式测试设计环境和环境设置实用程序
公开(公告)号：US06678875B2
公开(公告)日：2004-01-13
申请号：US10323979
申请日：2002-12-20
申请人： Brian John Pajak , Paul Price , Jean-François Côté , Luc Romain
发明人： Brian John Pajak , Paul Price , Jean-François Côté , Luc Romain
IPC分类号： G06F1750
CPC分类号： G01R31/318536 , G01R31/31704 , G01R31/318342 , G06F17/5045
摘要： An embedded test, chip design utility is an ease-of-use utility for assisting a circuit designer in quickly implementing a circuit embedded test design flow. Using the utility, a designer transforms a design netlist to include embedded test structures. The utility automatically builds a workspace containing a predetermined repository structure and design environment, generates control files for executing design automation tools that operate within the design flow, and encapsulates the data so as to be self-contained and easily transferable to other design teams.
摘要翻译：嵌入式测试芯片设计实用程序是一种易于使用的实用程序，用于帮助电路设计人员快速实现电路嵌入式测试设计流程。使用该实用程序，设计者将设计网表转换为包括嵌入式测试结构。该实用程序自动构建包含预定存储库结构和设计环境的工作空间，生成用于执行在设计流程中运行的设计自动化工具的控制文件，并封装数据，以便自包含并易于转移到其他设计团队。

2. 发明授权

US07103860B2 Verification of embedded test structures in circuit designs 有权
公开(公告)号：US07103860B2
公开(公告)日：2006-09-05
申请号：US10349452
申请日：2003-01-23
申请人： Paul Price , Jean-François Côté , Ajit Kumar Verma
发明人： Paul Price , Jean-François Côté , Ajit Kumar Verma
IPC分类号： G06F17/50
CPC分类号： G01R31/318314 , G01R31/318307 , G01R31/318357 , G06F17/5022
摘要： A program product for use in generating test benches for verifying test structures embedded in a circuit, comprises a verification specification processor for parsing a verification specification containing test specifications for selected test structures and a test bench generator for each of one or more types of embedded test structures, each test bench generator being operable to process a test structure specification of a test structure of a corresponding test structure type and generate a test bench using data contained in said test specifications of said verification specification, data contained in said test structure specification and data contained in a test connection specification.

3. 发明授权

US06725435B2 Method and program product for completing a circuit design having embedded test structures 失效
标题翻译：用于完成具有嵌入式测试结构的电路设计的方法和程序产品
公开(公告)号：US06725435B2
公开(公告)日：2004-04-20
申请号：US10323815
申请日：2002-12-20
申请人： Jean-François Côté , Paul Price
发明人： Jean-François Côté , Paul Price
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A sign-off method for use in verifying of embedded test structures in a circuit design extracts a description of all embedded test structures from a circuit description to create a test connection map file, and verifies the connections of the test structures to circuit pins or nets, creates verification configuration files for use, in performing a sign-off verification of the circuit, for a circuit containing logic test structures, verifies that each logic test structure complies with logic test design rules and creates logic test vectors and a reference signature, performs a formal verification and a static timing analysis of the circuit, generates a sign-off simulation test bench for each test structure using the verification configuration files and the test connection map file, executes the test benches to simulate all test structures in the circuit; and creates manufacturing test patterns.
摘要翻译：用于验证电路设计中嵌入式测试结构的签名方法从电路描述中提取所有嵌入式测试结构的描述，以创建测试连接映射文件，并验证测试结构与电路引脚或网络的连接，创建验证配置文件以供使用，在对包含逻辑测试结构的电路执行电路的签发验证时，验证每个逻辑测试结构符合逻辑测试设计规则并创建逻辑测试向量和参考签名，执行电路的正式验证和静态时序分析，使用验证配置文件和测试连接图文件为每个测试结构生成一个注销仿真测试台，执行测试台以模拟电路中的所有测试结构; 并创建制造测试模式。

4. 发明授权

US06868532B2 Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby 有权
标题翻译：用于设计用于静态电流测试的分层电路的方法和程序产品以及由此产生的电路
公开(公告)号：US06868532B2
公开(公告)日：2005-03-15
申请号：US10011128
申请日：2001-12-10
申请人： Benoit Nadeau-Dostie , Jean-François Côté
发明人： Benoit Nadeau-Dostie , Jean-François Côté
IPC分类号： G01R31/30 , G06F17/50
CPC分类号： G01R31/3012
摘要： A method of designing integrated circuits having an hierarchical structure for quiescent current testing, and the circuit which results therefrom is disclosed. The method comprises analyzing each of one or more selected hierarchical blocks independently of other selected blocks identify any circuit states of each block which could result in elevated quiescent current levels during quiescent current testing of the circuit, the analysis beginning with blocks at a lowest level of hierarchy and proceeding in sequence through each level of design hierarchy to a highest level of hierarchy containing a top-level block; and calculating a fault coverage for each selected block.
摘要翻译：一种设计具有用于静态电流测试的层次结构的集成电路的方法，以及由此产生的电路。该方法包括独立于其它所选块分析一个或多个选择的分层块中的每一个，识别每个块的任何电路状态，其可以导致电路的静态电流测试期间提高的静态电流电平，分析开始于最低级层次结构，并通过每个级别的设计层次顺序进行到包含顶级块的最高级别; 并计算每个所选块的故障覆盖。

5. 发明授权

US08619077B1 Efficient execution of color space processing functions in a graphics processing unit 有权
标题翻译：在图形处理单元中有效执行色彩空间处理功能
公开(公告)号：US08619077B1
公开(公告)日：2013-12-31
申请号：US10188093
申请日：2002-07-03
申请人： Jean-François Côté , Jean-Jacques Ostiguy
发明人： Jean-François Côté , Jean-Jacques Ostiguy
IPC分类号： G06T15/50 , G06T15/60 , G06T15/00
CPC分类号： G06T11/001 , G06T15/50 , G06T2200/28
摘要： A pixel shader program for execution by a processing unit in a graphics processing module is designed to execute a color space processing function on individual pixels of a video image. The color space processing function is broken down into series of steps, each of which is amenable to representation by an individual instruction taken from an instruction set. The instructions cause the processor to load pixel color data into first memory elements, to read the first memory elements as well as second memory elements containing pre-loaded parameters representative of the color space processing function and to generate a processed set of color data for each pixel by manipulating the first and second memory elements. In this way, color space processing functionality, such as color space conversion and procamp controls, is provided without the need for specialized hardware and without encroaching upon the computational efficiency of the host CPU.
摘要翻译：用于由图形处理模块中的处理单元执行的像素着色器程序被设计为对视频图像的各个像素执行色彩空间处理功能。颜色空间处理功能被分解成一系列步骤，每个步骤适合于从指令集获取的单独指令的表示。指令使处理器将像素颜色数据加载到第一存储器元件中，以读取第一存储器元件以及包含表示颜色空间处理功能的预加载参数的第二存储器元件，并且为每个存储器元件生成经处理的一组颜色数据通过操纵第一和第二存储元件来实现。以这种方式，可以提供色空间处理功能，例如色空间转换和前置控制，而不需要专门的硬件，而不会影响主机CPU的计算效率。

6. 发明授权

US08516317B2 Methods for at-speed testing of memory interface 有权
标题翻译：存储器接口的高速测试方法
公开(公告)号：US08516317B2
公开(公告)日：2013-08-20
申请号：US13018279
申请日：2011-01-31
申请人： Benoit Nadeau-Dostie , Jean-François Côté
发明人： Benoit Nadeau-Dostie , Jean-François Côté
IPC分类号： G01R31/28
CPC分类号： G11C29/50012 , G11C8/16 , G11C29/1201 , G11C29/32
摘要： Methods for at-speed testing of a memory interface associated with an embedded memory comprise two write operations in succession, two read operations in succession, and a capture operation using scan cells. The write and read operations are performed during a single clock burst, two separate clock bursts in a clock signal, or two separate clock bursts in separate clock signals.
摘要翻译：用于速度测试与嵌入式存储器相关联的存储器接口的方法包括连续的两个写入操作，连续的两个读取操作以及使用扫描单元的捕获操作。写和读操作在单个时钟脉冲串期间执行，时钟信号中有两个独立的时钟脉冲串，或者在分离的时钟信号中执行两个分离的时钟脉冲串。

7. 发明授权

US07617425B2 Method for at-speed testing of memory interface using scan 有权
标题翻译：使用扫描速度快速测试存储器接口的方法
公开(公告)号：US07617425B2
公开(公告)日：2009-11-10
申请号：US11439497
申请日：2006-05-24
申请人： Benoit Nadeau-Dostie , Jean-François Côté
发明人： Benoit Nadeau-Dostie , Jean-François Côté
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C29/50012 , G11C2029/0401 , G11C2029/3202
摘要： A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory locations were written; capturing output data from the memory interface; and analyzing captured output data to determine whether said captured output data corresponds to expected data.
摘要翻译：与半导体电路中的嵌入式存储器相关联的存储器接口的测试方法和电路涉及连续写入两个存储单元; 以写入两个存储器位置的相同顺序连续读取两个存储器位置; 从存储器接口捕获输出数据; 并分析所捕获的输出数据以确定所述捕获的输出数据是否对应于预期数据。

8. 发明授权

US07129962B1 Efficient video processing method and system 有权
标题翻译：高效的视频处理方法和系统
公开(公告)号：US07129962B1
公开(公告)日：2006-10-31
申请号：US10104011
申请日：2002-03-25
申请人： Jean-François Côté , Jean-Jacques Ostiguy
发明人： Jean-François Côté , Jean-Jacques Ostiguy
IPC分类号： G09G5/02
CPC分类号： H04N19/42 , G06F17/147 , H04N19/60
摘要： A graphics processing device for converting coefficients in a video data stream from a first type, e.g., frequency-domain, to a second type, e.g., color-domain. The device includes an input for receiving the video data stream including a set of coefficients of the first type and a storage medium holding a data structure containing a first set of coefficients of the second type. The device further includes a processor communicating with the input and with the storage medium. The processor uses the data structure to convert the set of coefficients of the first type to a second set of coefficients of the second type. The device also includes an output in communication with said processor, for releasing an output video data stream including the second set of coefficients of the second type. The same data structure is used repeatedly for each incoming set of coefficients of the first type, thus allowing a transform, such as an IDCT, to be computed efficiently.
摘要翻译：一种图形处理装置，用于将视频数据流中的系数从第一类型（例如，频域）转换为第二类型（例如，色域）。该装置包括用于接收视频数据流的输入，该视频数据流包括第一类型的一组系数，以及存储介质，该存储介质保持包含第二类型的第一组系数的数据结构。该设备还包括与输入端和存储介质通信的处理器。处理器使用数据结构将第一类型的系数集合转换成第二类型的第二组系数。该设备还包括与所述处理器通信的输出，用于释放包括第二类型的第二组系数的输出视频数据流。对于第一类型的每个传入的系数集合重复使用相同的数据结构，从而允许有效地计算诸如IDCT的变换。

9. 发明授权

US06829730B2 Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same 有权
标题翻译：设计具有多个测试接入端口的电路的方法，由此产生的电路及其使用方法
公开(公告)号：US06829730B2
公开(公告)日：2004-12-07
申请号：US09843307
申请日：2001-04-27
申请人： Benoit Nadeau-Dostie , Jean-François Côté
发明人： Benoit Nadeau-Dostie , Jean-François Côté
IPC分类号： G06F1127
CPC分类号： G01R31/318563 , G01R31/318555
摘要： In a circuit with multiple Test Access Port (TAP) interfaces, the TAPs are arranged into groups, with secondary TAPs in one or more groups and a master TAP in another group, the master TAP having an instruction register with bits for storing a group selection code; a Test Data Output (TDO) circuit responsive to the group selection code connects the group TDO of one of the groups to the circuit TDO; and, for each secondary TAP group, a group Test Data Input (TDI) circuit responsive to a shift state signal for selectively connecting the group TDI to the circuit TDI or to the output of a padding register having its input connected to the circuit TDI, and its output connected to an input of the group TDI circuit; and a group TMS circuit responsive to a predetermined TAP selection code associated with the group for producing a group TMS signal for each TAP in the group.
摘要翻译：在具有多个测试访问端口（TAP）接口的电路中，TAP被分成组，其中一个或多个组中的辅助TAP和另一个组中的主TAP，主TAP具有指令寄存器，其中存储组选择码; 响应于组选择代码的测试数据输出（TDO）电路将组中的一组的组TDO连接到电路TDO; 并且对于每个次级TAP组，响应于用于选择性地将组TDI连接到电路TDI或其输入连接到电路TDI的填充寄存器的输出的移位状态信号的组测试数据输入（TDI）电路，其输出连接到组TDI电路的输入端; 以及组TMS电路，其响应于与该组相关联的预定TAP选择代码，用于为该组中的每个TAP产生组TMS信号。

10. 发明授权

US06763489B2 Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description 有权
标题翻译：数字电路的扫描测试方法，与其一起使用的数字电路以及将测试方法纳入电路描述的程序产品
公开(公告)号：US06763489B2
公开(公告)日：2004-07-13
申请号：US09773541
申请日：2001-02-02
申请人： Benoit Nadeau-Dostie , Jean-François Côté
发明人： Benoit Nadeau-Dostie , Jean-François Côté
IPC分类号： G01R3128
CPC分类号： G01R31/318552 , G01R31/318563
摘要： A method for at-speed scan testing of circuits having scannable memory elements which source multi-cycle paths having propagation delays that are longer than the period of a system clock used during normal operation comprises loading a test stimulus into the scannable memory elements; performing a capture operation, including configuring in capture mode throughout the capture operation, non-source memory elements and multi-cycle path source memory elements which have a predetermined maximum capture clock rate which is the same as or higher than the clock rate of the capture clock; and configuring in a hold mode during all but the last cycle of the capture operation and in capture mode for the last cycle, source memory elements which have a predetermined maximum capture clock rate which is lower than the clock rate of the capture clock; applying at least two clock cycles of the capture clock; and unloading test response data captured by said scannable memory elements.
摘要翻译：一种用于对具有可扫描存储器元件的电路进行高速扫描测试的方法，所述可扫描存储器元件源于具有比在正常操作期间使用的系统时钟的周期长的传播延迟的多周期路径，包括将测试激励加载到可扫描存储器元件中; 执行捕获操作，包括在整个捕获操作期间以捕获模式配置，非源存储器元件和多周期路径源存储器元件，其具有与捕获的时钟速率相同或更高的预定最大捕获时钟速率时钟; 以及在捕捉操作的最后周期以及最后一个周期的捕获模式期间的所有除了最后周期之内的保持模式下进行配置，所述源存储器元件具有低于捕获时钟的时钟速率的预定最大捕获时钟速率; 应用捕获时钟的至少两个时钟周期; 以及卸载由所述可扫描存储器元件捕获的测试响应数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式