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2. 发明授权

US06615392B1 Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby 有权
标题翻译：分层设计和测试方法和系统，程序产品体现了由此产生的方法和集成电路
公开(公告)号：US06615392B1
公开(公告)日：2003-09-02
申请号：US09626877
申请日：2000-07-27
申请人： Benoit Nadeau-Dostie , Dwayne Burek , Jean-Francois Cote , Sonny Ngai San Shum , Pierre Girouard , Pierre Gauther , Sai Kennedy Vedantam , Luc Romain , Charles Bernard
发明人： Benoit Nadeau-Dostie , Dwayne Burek , Jean-Francois Cote , Sonny Ngai San Shum , Pierre Girouard , Pierre Gauther , Sai Kennedy Vedantam , Luc Romain , Charles Bernard
IPC分类号： G06F945
CPC分类号： G01R31/318591 , G01R31/318586
摘要： A method for use in the hierarchical design of integrated circuits having at least one module, each the module having functional memory elements and combinational logic, the method comprising reading in a description of the circuit; replacing the description of each functional memory element of the modules with a description of a scannable memory element configurable in scan mode and capture mode; partitioning each module into an internal partition and a peripheral partition by converting the description of selected scannable memory elements into a description of peripheral scannable memory elements which are configurable in an internal test mode, an external test mode and a normal operation mode; modifying the description of modules in the circuit description so as to arrange the memory elements into scan chains in which peripheral and internal scannable memory elements of each module are controlled by an associated module test controller when configured in internal test mode; and peripheral scannable memory elements of each module are controlled by a top-level test controller when configured in an external test mode; and verifying the correct operation of the internal test mode and the external test mode of the circuit.
摘要翻译：一种在具有至少一个模块的集成电路的分级设计中使用的方法，每个模块具有功能存储元件和组合逻辑，该方法包括读取电路的描述; 用扫描模式和捕获模式可配置的可扫描存储器元件的描述代替模块的每个功能存储元件的描述; 通过将所选择的可扫描存储器元件的描述转换为在内部测试模式，外部测试模式和正常操作模式中可配置的外围可扫描存储器元件的描述，将每个模块分成内部分区和外围分区; 修改电路描述中的模块的描述，以便将存储器元件布置成扫描链，其中当配置在内部测试模式中时，由模块测试控制器控制每个模块的外围和内部可扫描存储元件; 并且当在外部测试模式下配置时，每个模块的外围可扫描存储器元件由顶级测试控制器控制; 并验证电路的内部测试模式和外部测试模式的正确操作。

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