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1. 发明申请

US20100065841A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US20100065841A1
公开(公告)日：2010-03-18
申请号：US12555824
申请日：2009-09-09
申请人： Je-Hun LEE , Ki-Won KIM , Do-Hyun KIM , Woo-Geun LEE , Kap-Soo YOON
发明人： Je-Hun LEE , Ki-Won KIM , Do-Hyun KIM , Woo-Geun LEE , Kap-Soo YOON
IPC分类号： H01L29/786 , H01L21/34
CPC分类号： H01L27/1225 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02554 , H01L21/02565 , H01L23/53238 , H01L27/124 , H01L27/1248 , H01L27/1262 , H01L29/45 , H01L29/4908 , H01L29/513 , H01L29/518 , H01L29/66969 , H01L29/78603 , H01L29/7869 , H01L2924/0002 , H01L2924/00
摘要： A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.
摘要翻译： TFT阵列基板包括设置在绝缘基板上并包括沟道部分的半导体氧化物层，与半导体氧化物层重叠的栅极电极，插入在半导体氧化物层和栅电极之间的栅极绝缘层，以及设置在半导体氧化物层和栅电极。栅极绝缘层和钝化层中的至少一个包括氧氮化物层，并且氧氮化物层在氧氮化物层的位置更靠近半导体氧化物层的位置处具有比氮的浓度高的氧氮化物层。

2. 发明申请

US20130009151A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20130009151A1
公开(公告)日：2013-01-10
申请号：US13613566
申请日：2012-09-13
申请人： Je-Hun LEE , Ki-Won KIM , Do-Hyun KIM , Woo-Geun LEE , Kap-Soo YOON
发明人： Je-Hun LEE , Ki-Won KIM , Do-Hyun KIM , Woo-Geun LEE , Kap-Soo YOON
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1225 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02554 , H01L21/02565 , H01L23/53238 , H01L27/124 , H01L27/1248 , H01L27/1262 , H01L29/45 , H01L29/4908 , H01L29/513 , H01L29/518 , H01L29/66969 , H01L29/78603 , H01L29/7869 , H01L2924/0002 , H01L2924/00
摘要： A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

3. 发明申请

US20120211753A1 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE 有权
标题翻译：显示基板和制造显示基板的方法
公开(公告)号：US20120211753A1
公开(公告)日：2012-08-23
申请号：US13328658
申请日：2011-12-16
申请人： Ki-Won KIM , Je-Hun LEE , Sung-Haeng CHO , Woo-Geun LEE , Kap-Soo YOON , Do-Hyun KIM , Seung-Ha CHOI
发明人： Ki-Won KIM , Je-Hun LEE , Sung-Haeng CHO , Woo-Geun LEE , Kap-Soo YOON , Do-Hyun KIM , Seung-Ha CHOI
IPC分类号： H01L29/786 , H01L21/336 , H01L33/00
CPC分类号： H01L27/1225 , H01L27/1288
摘要： In a display substrate and a method of manufacturing the display substrate, the display substrate includes a data line, a channel pattern, an insulating pattern and a pixel electrode. The data line extends in a direction on a base substrate. The channel pattern is disposed in a separate region between an input electrode connected to the data line and an output electrode spaced apart from the input electrode. The channel pattern makes contact with the input electrode and the output electrode on the input and output electrodes. The insulating pattern is spaced apart from the channel pattern on the base substrate and includes a contact hole exposing the output electrode. The pixel electrode is formed on the insulating pattern to make contact with the output electrode through the contact hole. Thus, a damage of the oxide semiconductor layer may be minimized and a manufacturing process may be simplified.
摘要翻译：在显示基板和显示基板的制造方法中，显示基板包括数据线，通道图案，绝缘图案和像素电极。数据线沿着基底基板上的方向延伸。通道图案设置在与数据线连接的输入电极和与输入电极间隔开的输出电极之间的分离区域中。通道图案与输入电极和输出电极上的输出电极接触。绝缘图案与基底基板上的沟道图案间隔开，并且包括暴露输出电极的接触孔。像素电极形成在绝缘图案上，以通过接触孔与输出电极接触。因此，可以使氧化物半导体层的损伤最小化，并且可以简化制造工艺。

4. 发明申请

US20110193076A1 THIN FILM TRANSISTOR PANEL AND FABRICATING METHOD THEREOF 有权
标题翻译：薄膜晶体管面板及其制作方法
公开(公告)号：US20110193076A1
公开(公告)日：2011-08-11
申请号：US12957743
申请日：2010-12-01
申请人： Pil-Sang YUN , Ki-Won KIM , Hye-Young RYU , Woo-Geun LEE , Seung-Ha CHOI , Jae-Hyoung YOUN , Kyoung-Jae CHUNG , Young-Wook LEE , Je-Hun LEE , Kap-Soo YOON , Do-Hyun KIM , Dong-Ju YANG , Young-Joo CHOI
发明人： Pil-Sang YUN , Ki-Won KIM , Hye-Young RYU , Woo-Geun LEE , Seung-Ha CHOI , Jae-Hyoung YOUN , Kyoung-Jae CHUNG , Young-Wook LEE , Je-Hun LEE , Kap-Soo YOON , Do-Hyun KIM , Dong-Ju YANG , Young-Joo CHOI
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/41733 , H01L21/44 , H01L21/441 , H01L21/465 , H01L21/475 , H01L21/47573 , H01L21/47635 , H01L27/1214 , H01L27/1225 , H01L27/127 , H01L27/1288 , H01L29/66969 , H01L29/78606 , H01L29/7869 , H01L29/78696
摘要： A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
摘要翻译：薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的在蚀刻停止器上。

5. 发明申请

US20120286259A1 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：显示基板及其制造方法
公开(公告)号：US20120286259A1
公开(公告)日：2012-11-15
申请号：US13431448
申请日：2012-03-27
申请人： Jae-Woo PARK , Dong-Hoon LEE , Sung-Haeng CHO , Woo-Geun LEE , Kap-Soo YOON
发明人： Jae-Woo PARK , Dong-Hoon LEE , Sung-Haeng CHO , Woo-Geun LEE , Kap-Soo YOON
IPC分类号： H01L29/786 , H01L21/44
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/1288 , H01L29/66969
摘要： Exemplary embodiments of the present invention provide a display substrate including a gate electrode, an oxide semiconductor pattern, a source electrode, a drain electrode, and an etch stop pattern. The gate electrode may be disposed on a base substrate. The oxide semiconductor pattern may be disposed over the gate electrode. The source electrode may be disposed on the oxide semiconductor pattern. The drain electrode may be disposed on the oxide semiconductor pattern and spaced apart from the source electrode. The etch stop pattern may be disposed over the gate electrode, the etch stop pattern may be overlapping a space between the source electrode and the drain electrode and may include a metal oxide. The reliability of the display substrate may, therefore, be improved.
摘要翻译：本发明的示例性实施例提供了包括栅电极，氧化物半导体图案，源电极，漏电极和蚀刻停止图案的显示基板。栅电极可以设置在基底基板上。氧化物半导体图案可以设置在栅极上。源极可以设置在氧化物半导体图案上。漏极可以设置在氧化物半导体图案上并与源电极间隔开。蚀刻停止图案可以设置在栅电极之上，蚀刻停止图案可以与源电极和漏电极之间的空间重叠，并且可以包括金属氧化物。因此，可以提高显示基板的可靠性。

6. 发明申请

US20120037910A1 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示基板及其制造方法
公开(公告)号：US20120037910A1
公开(公告)日：2012-02-16
申请号：US13111027
申请日：2011-05-19
申请人： Young-Joo CHOI , Woo-Geun LEE , Do-Hyun KIM
发明人： Young-Joo CHOI , Woo-Geun LEE , Do-Hyun KIM
IPC分类号： H01L33/08 , H01L33/16
CPC分类号： H01L27/1225
摘要： A display substrate includes; a gate pattern including a gate electrode disposed on a substrate, a gate insulation layer disposed on the substrate and the gate pattern, an insulation pattern including; a first thickness part disposed on a first area of the gate insulation layer overlapping the gate electrode and a second thickness part disposed on a second area of the gate insulation layer adjacent to the first area, an oxide semiconductor pattern disposed on the first thickness part of the first area, an etch stopper disposed on the oxide semiconductor pattern, a source pattern including a source electrode and a drain electrode which contact the oxide semiconductor pattern, and a pixel electrode which contacts the drain electrode.
摘要翻译：显示基板包括：栅极图案，包括设置在基板上的栅极电极，设置在基板上的栅极绝缘层和栅极图案，绝缘图案，包括：设置在与栅电极重叠的栅极绝缘层的第一区域上的第一厚度部分和设置在与第一区域相邻的栅极绝缘层的第二区域上的第二厚度部分，设置在栅极绝缘层的第一厚度部分上的氧化物半导体图案第一区域，设置在氧化物半导体图案上的蚀刻停止件，包括与氧化物半导体图案接触的源电极和漏电极的源图案以及与漏电极接触的像素电极。

7. 发明申请

US20110168997A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US20110168997A1
公开(公告)日：2011-07-14
申请号：US13006591
申请日：2011-01-14
申请人： Young-Wook LEE , Woo-Geun LEE , Ki-Won KIM , Hyun-Jung LEE , Ji-Soo OH
发明人： Young-Wook LEE , Woo-Geun LEE , Ki-Won KIM , Hyun-Jung LEE , Ji-Soo OH
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/124 , H01L21/76834 , H01L27/1225 , H01L27/1255 , H01L27/1262 , H01L27/127 , H01L27/1288 , H01L29/7869 , H01L29/78693
摘要： A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode of a thin film transistor (TFT) together with the gate electrode, and a data line extending in a direction intersecting the gate line, and etch stop patterns disposed at an area where the TFT is formed between the source/drain electrodes and the oxide semiconductor layer pattern and at an area where the gate line and the data line overlap each other between the gate line and the data line.
摘要翻译：提供薄膜晶体管（TFT）阵列基板及其制造方法。 TFT阵列基板可以包括设置在基板上的栅极线，包括栅极线和栅电极，设置在栅电极上的氧化物半导体层图案，设置在氧化物半导体层图案上的数据线，并且包括源电极和薄膜晶体管（TFT）的漏电极和栅电极以及沿着与栅极线交叉的方向延伸的数据线，以及蚀刻停止图案，设置在源极/漏极之间形成TFT的区域，以及氧化物半导体层图案和栅极线与数据线在栅极线与数据线之间重叠的区域。

8. 发明申请

US20090302316A1 THIN FILM TRANSISTOR ARRAY PANEL 有权
标题翻译：薄膜晶体管阵列
公开(公告)号：US20090302316A1
公开(公告)日：2009-12-10
申请号：US12464920
申请日：2009-05-13
申请人： Woo-Geun LEE , Jae-Hyoung YOUN , Ki-Won KIM , Young-Wook LEE , Jong-In KIM
发明人： Woo-Geun LEE , Jae-Hyoung YOUN , Ki-Won KIM , Young-Wook LEE , Jong-In KIM
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/78696
摘要： A thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the gate line, a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor, a data line formed on the semiconductor and including a source electrode and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode.
摘要翻译：薄膜晶体管阵列面板包括基板，形成在基板上的栅极线，包括栅极电极，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上并包括薄膜晶体管的沟道的半导体，形成在半导体上的数据线，包括相对于薄膜晶体管的沟道形成在半导体上并与源电极相对的源电极和漏电极，其中薄膜晶体管的沟道覆盖两个侧表面的栅电极。

9. 发明申请

US20100182068A1 METHOD AND APPARATUS FOR ACCOUNTING FOR CHANGES IN TRANSISTOR CHARACTERISTICS 有权
标题翻译：用于会计变更的晶体管特性的方法和装置
公开(公告)号：US20100182068A1
公开(公告)日：2010-07-22
申请号：US12357261
申请日：2009-01-21
申请人： Woo-Geun LEE , Jean-Ho Song , Yeong-Keun Kwon , Min-Cheol Lee , Ki-Won Kim , Young-Wook Lee
发明人： Woo-Geun LEE , Jean-Ho Song , Yeong-Keun Kwon , Min-Cheol Lee , Ki-Won Kim , Young-Wook Lee
IPC分类号： G06G7/12
CPC分类号： G09G3/3648 , G09G2300/0413 , G09G2300/0819 , G09G2320/043
摘要： A device for accounting for changes in characteristics of a transistor is presented. The device includes a transistor and a comparator receiving a feedback signal from the transistor and a reference signal. The comparator provides an output to a bias voltage generator. The bias voltage generator includes an input connected to the output of the comparator and an output connected to the transistor. In some embodiments of the invention the transistor is a double gate transistor and the bias voltage generator is applied to a top gate of the double gate transistor in order to control characteristics of the transistor such as turn on voltage.
摘要翻译：提出了一种用于考虑晶体管特性变化的装置。该器件包括晶体管和比较器，其接收来自晶体管的反馈信号和参考信号。比较器向偏置电压发生器提供输出。偏置电压发生器包括连接到比较器的输出的输入端和连接到晶体管的输出。在本发明的一些实施例中，晶体管是双栅极晶体管，并且偏置电压发生器被施加到双栅晶体管的顶栅，以便控制晶体管的特性，例如导通电压。

10. 发明申请

US20120037906A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US20120037906A1
公开(公告)日：2012-02-16
申请号：US13115088
申请日：2011-05-24
申请人： Hye-Young RYU , Woo-Geun LEE , Young-Joo CHOI , Kyoung-Jae CHUNG , Jin-Won LEE , Seung-Ha CHOI , Hee-Jun BYEON , Pil-Sang YUN
发明人： Hye-Young RYU , Woo-Geun LEE , Young-Joo CHOI , Kyoung-Jae CHUNG , Jin-Won LEE , Seung-Ha CHOI , Hee-Jun BYEON , Pil-Sang YUN
IPC分类号： H01L29/786 , H01L21/44
CPC分类号： H01L27/1214 , H01L27/1225 , H01L27/1255
摘要： A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.
摘要翻译：提供了能够降低由于氧化物半导体图案的劣化引起的器件劣化的薄膜晶体管阵列基板及其制造方法。薄膜晶体管阵列基板可以包括其上形成有栅极的绝缘基板，形成在绝缘基板上的栅极绝缘膜，设置在栅极绝缘膜上的氧化物半导体图案，形成在氧化物半导体上的抗蚀刻图案图案，以及形成在防蚀刻图案上的源电极和漏电极。氧化物半导体图案可以包括位于源电极和漏电极之间的边缘部分，并且边缘部分可以包括至少一个导电区域和至少一个非导电区域。

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