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1. 发明授权

US07024327B1 Techniques for automatically generating tests for programmable circuits 失效
标题翻译：自动生成可编程电路测试的技术
公开(公告)号：US07024327B1
公开(公告)日：2006-04-04
申请号：US10323506
申请日：2002-12-18
申请人： Jayabrata Ghosh Dastidar , Adam Wright , Hung Hing Anthony Pang , Binh Vo , Ajay Nagarandal , Paul J. Tracy , Michael Harms
发明人： Jayabrata Ghosh Dastidar , Adam Wright , Hung Hing Anthony Pang , Binh Vo , Ajay Nagarandal , Paul J. Tracy , Michael Harms
IPC分类号： G01R31/00 , G01R31/14
CPC分类号： G01R31/318314 , G01R31/318307
摘要： Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmable interconnections and functions as nodes. Tests routes are generated that connect the nodes in the connectivity graph between control points and observation points on the programmable circuit. The routes are grouped into configuration patterns that can be tested in one test cycle. Test vectors are then applied to the routes to determine if the interconnects and circuit functions are operable. Systems and methods of the present invention automatically create test patterns for a programmable circuit to reduce engineer time. The present invention also reduces test time and resources by increasing the number of interconnections and circuit elements tested in each configuration pattern.
摘要翻译：可编程电路具有连接可编程电路元件的可编程互连结构。对可编程电路元件和可编程电路的互连可以自动生成测试图案。连接图表示可编程互连并作为节点。生成测试路线，连接可控电路上的控制点和观测点之间的连接图中的节点。路由被分组成可以在一个测试周期中测试的配置模式。然后将测试向量应用于路由以确定互连和电路功能是否可操作。本发明的系统和方法自动创建可编程电路的测试模式，以减少工程师的时间。本发明还通过增加在每个配置模式中测试的互连和电路元件的数量来减少测试时间和资源。

2. 发明授权

US07409669B1 Automatic test configuration generation facilitating repair of programmable circuits 失效
标题翻译：自动测试配置生成便于修复可编程电路
公开(公告)号：US07409669B1
公开(公告)日：2008-08-05
申请号：US10459187
申请日：2003-06-10
申请人： Jayabrata Ghosh Dastidar , Paul J. Tracy , Adam Wright
发明人： Jayabrata Ghosh Dastidar , Paul J. Tracy , Adam Wright
IPC分类号： G06F17/50
CPC分类号： G01R31/318516
摘要： Techniques are provided that control the generation of test routes to improve the ability of a test system to isolate defects on programmable circuits. A test generator creates test routes that test the horizontal resources. In these test routes, the inputs of each circuit element are only connected to other circuit elements in the same row. Test routes are also generated to test the vertical resources. Each of theses test routes is allowed to make only one transition from between two different rows of circuit elements. The configuration generator includes a post processor that ensures all source drivers in the test routes connect to at least two sinks.
摘要翻译：提供了技术来控制测试路线的产生，以提高测试系统隔离可编程电路上的缺陷的能力。测试生成器创建测试水平资源的测试路由。在这些测试路线中，每个电路元件的输入仅与同一行中的其他电路元件连接。还生成测试路线以测试垂直资源。这些测试路线中的每一条允许仅从两行不同的电路元件之间仅进行一次转换。配置生成器包括后处理器，其确保测试路由中的所有源驱动器连接至少两个汇。

3. 发明授权

US08516322B1 Automatic test pattern generation system for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的自动测试图生成系统
公开(公告)号：US08516322B1
公开(公告)日：2013-08-20
申请号：US12568136
申请日：2009-09-28
申请人： Jayabrata Ghosh Dastidar , Alok Shreekant Doshi , Binh Vo , Kalyana Ravindra Kantipudi , Sergey Timokhin
发明人： Jayabrata Ghosh Dastidar , Alok Shreekant Doshi , Binh Vo , Kalyana Ravindra Kantipudi , Sergey Timokhin
IPC分类号： G01R31/3183 , G01R31/40
CPC分类号： G01R31/3183
摘要： A programmable integrated circuit may contain multiple logic blocks. Computing equipment may be used to run automated tools that process a design for the programmable integrated circuit to perform corresponding circuit tests. A translation tool may translate a transistor-level description of circuitry on the programmable integrated circuit into a gate-level description. A block-level test configuration data generation tool may generate block-level test configuration data files. The test configuration data files may be used as constraints for an automatic test pattern generation tool that produces block-level test vectors. A full-chip propagation tool may use the block-level test vectors, block-level test configuration data files, and full-chip constraints to produce corresponding full-chip test configuration data and full-chip test vectors for testing the integrated circuit. A translation tool may convert the configuration data and test vectors into a tester file.
摘要翻译：可编程集成电路可以包含多个逻辑块。计算设备可用于运行自动化工具，处理可编程集成电路的设计以执行相应的电路测试。翻译工具可以将可编程集成电路上的电路的晶体管级描述转换成门级描述。块级测试配置数据生成工具可以生成块级测试配置数据文件。测试配置数据文件可以用作产生块级测试向量的自动测试模式生成工具的约束。全芯片传播工具可以使用块级测试向量，块级测试配置数据文件和全芯片约束来产生相应的全芯片测试配置数据和用于测试集成电路的全芯片测试向量。翻译工具可将配置数据和测试向量转换为测试文件。

4. 发明授权

US07062685B1 Techniques for providing early failure warning of a programmable circuit 失效
标题翻译：提供可编程电路的早期故障警告的技术
公开(公告)号：US07062685B1
公开(公告)日：2006-06-13
申请号：US10317436
申请日：2002-12-11
申请人： Jordan Plofsky , Jayabrata Ghosh Dastidar , Michael Harms
发明人： Jordan Plofsky , Jayabrata Ghosh Dastidar , Michael Harms
IPC分类号： G06F11/00
CPC分类号： G01R31/318516 , G06F11/1423 , H03K19/177 , H03K19/17736
摘要： Techniques for monitoring the performance of a programmable circuit and to provide an early warning of a potential failure are provided. A processor monitors the performance of components on a programmable circuit over time. The processor stores performance characteristics for the components in memory. If the performance characteristics for particular components fall outside tolerance ranges, these components may to fail to operate according to specifications. Once the performance characteristics for particular components are outside the tolerance ranges, the processor sends out an alert signal. The alert signal indicates the possibility that the performance of the programmable circuit may violate the specifications in the future. The processor may repair the programmable circuit by re-routing around the problem components.
摘要翻译：提供了用于监视可编程电路的性能并提供潜在故障的早期警告的技术。处理器随时间监视可编程电路上的组件的性能。处理器存储内存中组件的性能特征。如果特定部件的性能特性落在公差范围之外，这些部件可能无法根据规格进行操作。一旦特定组件的性能特征超出公差范围，处理器就会发出警报信号。警报信号表示可编程电路的性能可能会违反将来的规格。处理器可以通过围绕问题组件重新路由来修复可编程电路。

5. 发明授权

US07058534B1 Method and apparatus for application specific test of PLDs 失效
标题翻译： PLD应用特异性检测方法和装置
公开(公告)号：US07058534B1
公开(公告)日：2006-06-06
申请号：US10394486
申请日：2003-03-19
申请人： Paul Tracy , Michael Harms , Jayabrata Ghosh Dastidar , Steven Perry
发明人： Paul Tracy , Michael Harms , Jayabrata Ghosh Dastidar , Steven Perry
IPC分类号： G01R31/00
CPC分类号： G01R31/318516
摘要： Method and apparatus for application specific testing of PLDs. The PLD has a number of resources, less than all of which are used for implementing a customer application. The method includes the following steps. The set of resources that is used for implementing the customer application is identified. A test is then performed only on the set and a test result is generated. Defective resources may be replaced. The PLD is identified as defective only if one of the resources associated with the customer application is defective. Such application specific testing allows the ability of the customer to perform in-system testing, the reduction of the time required for testing the PLD, and the testing of PLDs based on knowledge of the customer's application, among other advantages.
摘要翻译： PLD应用特定测试方法和设备。 PLD具有多个资源，少于用于实施客户应用程序的资源。该方法包括以下步骤。识别用于实现客户应用程序的一组资源。然后仅对集合进行测试，并生成测试结果。资源不足可能会被替换。只有当与客户应用程序相关联的资源之一有缺陷时，PLD才被识别为有缺陷。这样的应用程序特定测试允许客户执行系统测试，减少测试PLD所需的时间以及基于客户应用知识的PLD测试的能力等。

6. 发明授权

US07111213B1 Failure isolation and repair techniques for integrated circuits 有权
标题翻译：集成电路故障隔离和修复技术
公开(公告)号：US07111213B1
公开(公告)日：2006-09-19
申请号：US10316607
申请日：2002-12-10
申请人： Jayabrata Ghosh Dastidar , Michael Harms
发明人： Jayabrata Ghosh Dastidar , Michael Harms
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318516 , G01R31/318533
摘要： Techniques for isolating and repairing failures on a programmable circuit are provided. An error on programmable circuit may be caused by a defect on the chip. The error is located, and the circuit elements effected by the defect are isolated. By identifying operable circuit elements near the defect, the number of circuit elements that are adversely effected by the defected can be narrowed down. The failed circuit elements adversely effected by the defect are then shut down and cut off from the rest of the programmable circuit. The functionality performed by the failed circuit elements is transferred to an unused portion of the programmable circuit. The se techniques reduce the amount of circuit elements that need to be shut down as a result of a defect on a programmable circuit.
摘要翻译：提供了在可编程电路上分离和修复故障的技术。可编程电路的错误可能由芯片上的缺陷引起。定位错误，由缺陷影响的电路元件被隔离。通过识别缺陷附近的可操作的电路元件，可以缩小由缺陷引起的不利影响的电路元件的数量。然后由缺陷不利地影响的故障电路元件被关闭并与可编程电路的其余部分切断。由故障电路元件执行的功能被传送到可编程电路的未使用部分。该技术减少了由于可编程电路上的缺陷而需要关闭的电路元件的数量。

7. 发明授权

US08621303B1 Clock control circuitry and methods of utilizing the clock control circuitry 有权
公开(公告)号：US08621303B1
公开(公告)日：2013-12-31
申请号：US13354706
申请日：2012-01-20
申请人： Kalyana Ravindra Kantipudi , Dhwani Shah , Jayabrata Ghosh Dastidar
发明人： Kalyana Ravindra Kantipudi , Dhwani Shah , Jayabrata Ghosh Dastidar
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/31727 , G01R31/318536 , G01R31/318555 , G01R31/318572 , G06F1/04
摘要： A design-for-test (DFT) circuitry is disclosed. The DFT circuitry includes a first multiplexer operable to transfer one of a clock signal or an inverted clock signal based on a clock polarity control signal. The DFT circuitry also includes a burst counter coupled to the first multiplexer. The burst counter is operable to output a signal at a first logic state for a predefined pulse count. The DFT circuitry also includes a second multiplexer that is operable to output one of the clock polarity control signal or the clock signal according to a signal output from the burst counter. The DFT circuitry may also include a third multiplexer that forwards control signals identifying the predefined pulse count to the burst counter from different sources such as an external pin, a programmable interconnect, and a memory element.

8. 发明授权

US07266028B1 Method and apparatus for bit mapping memories in programmable logic device integrated circuits during at-speed testing 有权
标题翻译：用于在速度测试期间可编程逻辑器件集成电路中位映射存储器的方法和装置
公开(公告)号：US07266028B1
公开(公告)日：2007-09-04
申请号：US11357253
申请日：2006-02-16
申请人： Jayabrata Ghosh Dastidar
发明人： Jayabrata Ghosh Dastidar
IPC分类号： G11C7/00
CPC分类号： G11C29/44 , G11C2029/0401 , G11C2029/0405 , G11C2029/1208 , G11C2029/1806 , G11C2029/3602 , H03K19/1776 , H03K19/17764
摘要： Programmable logic devices may use shadow memory for gathering diagnostic information while testing memory blocks. Memory block testing may be performed at any clock speed allowed during normal operation in a system such as the highest allowed clock speed. Built in self test circuitry and address and data paths are formed by loading configuration data into a programmable logic device. During write operations on a memory block under test, test data words are written into the memory block. A comparator compares data words read from the memory block to expected data words received from the test pattern generator to produce corresponding comparison data words. The comparison data words are written into the shadow memory. The same addresses are applied to the memory block under test and the shadow memory, so the stored comparison data words form a test results bit map indicative of errors in the memory block.
摘要翻译：可编程逻辑器件可以在测试存储器块时使用影子存储器来收集诊断信息。可以在诸如最高允许时钟速度的系统中的正常操作期间允许的任何时钟速度下执行存储器块测试。内置自检电路，地址和数据路径是通过将配置数据加载到可编程逻辑器件中形成的。在对被测内存块进行写操作期间，将测试数据字写入存储块。比较器将从存储器块读取的数据字与从测试码型发生器接收到的预期数据字进行比较，以产生对应的比较数据字。比较数据字被写入阴影存储器。相同的地址被应用于被测存储块和影子存储器，所以存储的比较数据字形成指示存储器块中的错误的测试结果位图。

9. 发明授权

US07131043B1 Automatic testing for programmable networks of control signals 有权
标题翻译：自动测试控制信号的可编程网络
公开(公告)号：US07131043B1
公开(公告)日：2006-10-31
申请号：US10671891
申请日：2003-09-25
申请人： Jayabrata Ghosh Dastidar
发明人： Jayabrata Ghosh Dastidar
IPC分类号： G01R31/28
CPC分类号： G01R31/31722 , G01R31/31723 , G01R31/318516
摘要： Techniques are provided for testing routing resources that route control signals on programmable integrated circuits (ICs). Control signals (such as clock signals) are routed through a logic gate to a test register. Values of the control signals are stored in the test register, transmitted outside the IC, and then compared to expected values to identify defects in the programmable interconnections. An enable circuit couples the control signals to functional registers on the programmable IC during user mode. The enable circuit decouples the control signals from the functional registers so that the control signals do not interfere with tests of the functional registers during test mode. During the test procedures, the control signals are treated as data signals and are not used to control other registers on the IC.
摘要翻译：提供了用于测试在可编程集成电路（IC）上路由控制信号的路由资源的技术。控制信号（例如时钟信号）通过逻辑门路由到测试寄存器。控制信号的值存储在测试寄存器中，在IC外传输，然后与预期值进行比较，以识别可编程互连中的缺陷。在用户模式期间，使能电路将控制信号耦合到可编程IC上的功能寄存器。使能电路将控制信号与功能寄存器分离，使得控制信号在测试模式期间不干扰功能寄存器的测试。在测试过程中，控制信号被视为数据信号，不用于控制IC上的其他寄存器。

10. 发明授权

US08952713B1 Method and apparatus for die testing 有权
标题翻译：模具测试的方法和设备
公开(公告)号：US08952713B1
公开(公告)日：2015-02-10
申请号：US13369224
申请日：2012-02-08
申请人： Jayabrata Ghosh Dastidar , Aman Aflaki Beni , Zunhang Yu Kasnavi
发明人： Jayabrata Ghosh Dastidar , Aman Aflaki Beni , Zunhang Yu Kasnavi
IPC分类号： G01R31/20
CPC分类号： G01R31/2886
摘要： A device tester is provided. The device tester includes a probe card and a substrate coupled to the probe card. The substrate has a plurality of layers for routing a signal. An integrated circuit is coupled to the substrate. The integrated circuit is operable to transmit an input signal received from a testing apparatus to a device under test through the substrate to a signal probe. The signal probe is further operable to receive a test signal from the device under test in response to the input signal, wherein the integrated circuit is operable to amplify the test signal, and transmit the amplified test signal to the testing apparatus.
摘要翻译：提供了一个设备测试仪。器件测试器包括探针卡和耦合到探针卡的衬底。衬底具有用于布线信号的多个层。集成电路耦合到衬底。集成电路可操作以将从测试装置接收的输入信号通过衬底传送到被测器件到信号探头。信号探头还可操作以响应于输入信号从被测器件接收测试信号，其中集成电路可操作以放大测试信号，并将放大的测试信号发送到测试设备。

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