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1. 发明申请

US20050040480A1 Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors 有权
标题翻译：热氮分配方法提高高掺杂超薄栅极电容器的均匀性
公开(公告)号：US20050040480A1
公开(公告)日：2005-02-24
申请号：US10652307
申请日：2003-09-02
申请人： Jay Burnham , James Nakos , James Quinlivan , Steven Shank , Deborah Tucker , Beth Ward
发明人： Jay Burnham , James Nakos , James Quinlivan , Steven Shank , Deborah Tucker , Beth Ward
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L21/318 , H01L29/51 , H01L29/76
CPC分类号： H01L21/28202 , H01L21/28185 , H01L21/28211 , H01L21/3144 , H01L21/31612 , H01L21/3185 , H01L29/513 , H01L29/518
摘要： Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.
摘要翻译：使用诸如远程等离子体氮化（RPN）的方法将氮气引入栅极介电层。然而，这些方法产生氮化层，其中层的横截面轮廓和氮分布都不均匀。使氮化层进行额外的NO退火工艺增加了氮化层的均匀性。

2. 发明申请

US20050048705A1 METHOD FOR FABRICATING A NITRIDED SILICON-OXIDE GATE DIELECTRIC 有权
标题翻译：氮化硅氧化物电介质的制备方法
公开(公告)号：US20050048705A1
公开(公告)日：2005-03-03
申请号：US10604905
申请日：2003-08-26
申请人： Jay Burnham , James Nakos , James Quinlivan , Bernie Roque , Steven Shank , Beth Ward
发明人： Jay Burnham , James Nakos , James Quinlivan , Bernie Roque , Steven Shank , Beth Ward
IPC分类号： H01L20060101 , H01L21/31 , H01L21/336 , H01L21/469
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/3144 , H01L29/518
摘要： A method of fabricating a gate dielectric layer, including: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.
摘要翻译：一种制造栅极电介质层的方法，包括：提供衬底; 在所述基板的顶表面上形成二氧化硅层; 在还原气氛中进行等离子体氮化，将二氧化硅层转换成氮氧化硅层。如此形成的电介质层可用于制造MOSFET。

3. 发明申请

US20080014692A1 METHOD FOR FABRICATING A NITRIDED SILICON-OXIDE GATE DIELECTRIC 有权
标题翻译：氮化硅氧化物电介质的制备方法
公开(公告)号：US20080014692A1
公开(公告)日：2008-01-17
申请号：US11778238
申请日：2007-07-16
申请人： Jay Burnham , James Nakos , James Quinlivan , Bernie Roque , Steven Shank , Beth Ward
发明人： Jay Burnham , James Nakos , James Quinlivan , Bernie Roque , Steven Shank , Beth Ward
IPC分类号： H01L21/336
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/3144 , H01L29/518
摘要： A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.
摘要翻译：一种制造栅极电介质层的方法。该方法包括：提供衬底; 在所述基板的顶表面上形成二氧化硅层; 在还原气氛中进行等离子体氮化，将二氧化硅层转换成氮氧化硅层。如此形成的电介质层可用于制造MOSFET。

4. 发明申请

US20050112888A1 Semiconductor metal contamination reduction for ultra-thin gate dielectrics 失效
标题翻译：用于超薄栅极电介质的半导体金属污染减少
公开(公告)号：US20050112888A1
公开(公告)日：2005-05-26
申请号：US10981232
申请日：2004-11-04
申请人： Jay Burnham , James Elliott , Kenneth Gault , Mousa Ishaq , Steven Shank , Mary St. Lawrence
发明人： Jay Burnham , James Elliott , Kenneth Gault , Mousa Ishaq , Steven Shank , Mary St. Lawrence
IPC分类号： H01L21/28 , H01L21/306 , H01L21/8238 , H01L29/51 , H01L21/302 , H01L21/461
CPC分类号： H01L21/28194 , H01L21/02046 , H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , Y10S257/913
摘要： A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.
摘要翻译：提供了用于大大减少或消除随后的多晶硅沉积期间形成的金属污染物的双层电介质结构。双层电介质结构包括位于底表面区域顶部富含氯的上表面区域。富含氯的上表面区域除去在随后形成多晶硅层期间存在于结构顶部的金属污染物。还提供了形成双层结构的方法。

5. 发明申请

US20060073688A1 GATE STACKS 失效
标题翻译：门盖
公开(公告)号：US20060073688A1
公开(公告)日：2006-04-06
申请号：US10711742
申请日：2004-10-01
申请人： Dale Martin , Steven Shank , Michael Triplett , Deborah Tucker
发明人： Dale Martin , Steven Shank , Michael Triplett , Deborah Tucker
IPC分类号： H01L21/3205
CPC分类号： H01L21/28247 , H01L21/28035 , H01L29/4916 , Y10S257/90
摘要： A structure and fabrication method for a gate stack used to define source/drain regions in a semiconductor substrate. The method comprises (a) forming a gate dielectric layer on top of the substrate, (b) forming a gate polysilicon layer on top of the gate dielectric layer, (c) implanting n-type dopants in a top layer of the gate polysilicon layer, (d) etching away portions of the gate polysilicon layer and the gate dielectric layer so as to form a gate stack on the substrate, and (e) thermally oxidizing side walls of the gate stack with the presence of a nitrogen-carrying gas. As a result, a diffusion barrier layer is formed at the same depth in the polysilicon material of the gate stack regardless of the doping concentration. Therefore, the n-type doped region of the gate stack has the same width as that of the undoped region of the gate stack.
摘要翻译：用于限定半导体衬底中的源极/漏极区域的栅堆叠的结构和制造方法。该方法包括：（a）在衬底的顶部形成栅介质层，（b）在栅极介电层的顶部形成栅极多晶硅层，（c）在栅极多晶硅层的顶层中注入n型掺杂剂，（d）蚀刻掉栅极多晶硅层和栅极电介质层的部分，以在衬底上形成栅极堆叠，以及（e）在存在氮气的气体下热氧化栅极堆叠的侧壁。结果，无论掺杂浓度如何，在栅叠层的多晶硅材料中，在相同的深度处形成扩散阻挡层。因此，栅极堆叠的n型掺杂区域具有与栅极堆叠的未掺杂区域相同的宽度。

6. 发明申请

US20060063326A1 Chemical mechanical polishing method 有权
标题翻译：化学机械抛光方法
公开(公告)号：US20060063326A1
公开(公告)日：2006-03-23
申请号：US10710604
申请日：2004-07-23
申请人： Garth Brooks , Bruce Porth , Steven Shank , Eric White
发明人： Garth Brooks , Bruce Porth , Steven Shank , Eric White
IPC分类号： H01L21/8242 , H01L21/302
CPC分类号： H01L27/10867 , H01L21/3212
摘要： A method of forming a structure, an array of structures and a memory cell, the method of fabricating a structure, including: (a) forming a trench in a substrate; (b) depositing a first layer of polysilicon on a surface of the substrate, the first layer of polysilicon filling the trench; (c) chemical-mechanical-polishing the first layer of polysilicon at a first temperature to expose the surface of the substrate; (d) removing an upper portion of the first polysilicon from the trench; (e) depositing a second layer of polysilicon on the surface of the substrate, the second layer of polysilicon filling the trench; and (f) chemical-mechanical-polishing the second layer of polysilicon at a second temperature to expose the surface of the substrate, the second temperature different from the first temperature.
摘要翻译：一种形成结构，结构阵列和存储单元的方法，制造结构的方法，包括：（a）在衬底中形成沟槽; （b）在所述衬底的表面上沉积第一层多晶硅，所述第一层多晶硅填充所述沟槽; （c）在第一温度下化学机械抛光所述第一层多晶硅以暴露所述衬底的表面; （d）从沟槽去除第一多晶硅的上部; （e）在所述衬底的表面上沉积第二层多晶硅，所述第二层多晶硅填充所述沟槽; 和（f）在第二温度下对所述第二层多晶硅进行化学机械抛光以暴露所述衬底的表面，所述第二温度不同于所述第一温度。

7. 发明申请

US20120167316A1 Sweeper Brush Frame with Adjustable Hood 审中-公开
标题翻译：带可调式罩的清扫刷框架
公开(公告)号：US20120167316A1
公开(公告)日：2012-07-05
申请号：US13300559
申请日：2011-11-19
申请人： R. Dane Davis , Robert Sikorski , Steven Shank , Jamie Davis
发明人： R. Dane Davis , Robert Sikorski , Steven Shank , Jamie Davis
IPC分类号： A47L11/24 , A46B13/02
CPC分类号： E01H5/098
摘要： A sweeper apparatus includes a brush frame with first and second sides and a top surface. A brush roll is supported on the brush frame and is adapted for rotation to dislodge snow or other debris from an associated surface. A brush hood is connected to the brush frame and includes a hood surface located between the top surface and the brush roll. The hood surface extends between the first and second lateral sides of the brush frame and is selectively movable between an up position and a down position. A stripper bar is connected to the brush hood and is movable with the hood surface when the hood surface moves between its down and up positions. At least one actuator is operably connected between the brush frame and the brush hood and is selectively operable to move the hood surface between its up and down positions.
摘要翻译：清扫装置包括具有第一和第二侧面的刷框架和顶面。刷辊支撑在刷架上并且适于旋转以从相关联的表面移除雪或其他碎屑。刷罩连接到刷框架，并且包括位于顶表面和刷辊之间的罩表面。罩表面在刷框架的第一和第二横向侧面之间延伸，并且可选择性地在上部位置和下部位置之间移动。脱模杆连接到刷罩，并且当发动机罩表面在其向下和向上位置之间移动时可以与发动机罩表面一起移动。至少一个致动器可操作地连接在刷框架和刷罩之间，并且可选择性地可操作地使罩表面在其上下位置之间移动。

8. 发明申请

US20080035978A1 METHOD TO ELIMINATE ARSENIC CONTAMINATION IN TRENCH CAPACITORS 失效
公开(公告)号：US20080035978A1
公开(公告)日：2008-02-14
申请号：US11875503
申请日：2007-10-19
申请人： Marshall Fleming , Mousa Ishaq , Steven Shank , Michael Triplett
发明人： Marshall Fleming , Mousa Ishaq , Steven Shank , Michael Triplett
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.

9. 发明申请

US20060091441A1 METHOD TO ELIMINATE ARSENIC CONTAMINATION IN TRENCH CAPACITORS 失效
标题翻译：消除电容式电容器中的污染物的方法
公开(公告)号：US20060091441A1
公开(公告)日：2006-05-04
申请号：US11276024
申请日：2006-02-10
申请人： Marshall Fleming , Mousa Ishaq , Steven Shank , Michael Triplett
发明人： Marshall Fleming , Mousa Ishaq , Steven Shank , Michael Triplett
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.
摘要翻译：提供了一种沟槽电容器结构，其中砷污染被基本上减少和/或基本上从通过具有高纵横比的沟槽开口的侧壁扩散到半导体衬底中被消除。本发明还提供一种制造这种沟槽电容器结构的方法以及在驱动退火步骤期间检测砷污染的方法。通过生产线运行的产品中砷的检测采用砷增强氧化的作用。也就是说，监测用于将砷驱入半导体衬底的高温氧化退火的厚度。对于大量的砷扩散，氧化速率将增加，导致较厚的氧化物层。如果检测到这样的事件，则可以重新加工已经通过工艺步骤形成掩埋板直到驱动退火的产品，以减少砷的污染。

10. 发明申请

US20060081556A1 DEEP TRENCH FORMATION IN SEMICONDUCTOR DEVICE FABRICATION 失效
标题翻译：半导体器件制造中的深层形成
公开(公告)号：US20060081556A1
公开(公告)日：2006-04-20
申请号：US10711953
申请日：2004-10-15
申请人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey Maling , Lisa Ninomiya , Bruce Porth , Steven Shank , Jessica Trapasso
发明人： June Cline , Dinh Dang , Mark Lagerquist , Jeffrey Maling , Lisa Ninomiya , Bruce Porth , Steven Shank , Jessica Trapasso
IPC分类号： H01B13/00 , B44C1/22
CPC分类号： H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要： A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.
摘要翻译：一种用于蚀刻半导体衬底中的深沟槽的方法。该方法包括以下步骤：（a）在半导体衬底的顶部上形成硬掩模层，（b）蚀刻硬掩模层中的硬掩模开口，以通过硬掩模层开口将半导体衬底暴露于大气中其中蚀刻硬掩模开口的步骤包括蚀刻硬掩模开口的底部以使得硬掩模开口的底部的侧壁基本垂直的步骤，以及（c）蚀刻硬掩模开口的底部的深沟槽基板通过硬掩模开口。

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