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1. 发明授权

US07166904B2 Structure and method for local resistor element in integrated circuit technology 有权
标题翻译：集成电路技术中局部电阻元件的结构与方法
公开(公告)号：US07166904B2
公开(公告)日：2007-01-23
申请号：US10708023
申请日：2004-02-03
申请人： Jason P. Gill , Terence B. Hook , Randy W. Mann , William J. Murphy , William R. Tonti , Steven H. Voldman
发明人： Jason P. Gill , Terence B. Hook , Randy W. Mann , William J. Murphy , William R. Tonti , Steven H. Voldman
IPC分类号： H01L29/00
CPC分类号： H01L27/11 , H01L27/0288 , H01L27/0802 , H01L27/1112 , H01L27/1203 , H01L29/7304 , H01L29/7378 , H01L29/7391 , H01L29/78 , Y10S257/903 , Y10S257/904
摘要： A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.
摘要翻译：一种用于形成具有优异的ESD保护特性的半导体器件的方法和系统。电阻材料层设置在触头螺柱上下表面中的至少一个上的接触孔内。在优选实施例中，积分电阻器的电阻值介于约1欧姆至约10欧姆之间，或10欧姆至100欧姆之间。电阻层的实施例包括溅射硅材料，隧道氧化物，隧道氮化物，硅注入氧化物，注入硅的氮化物或非晶多晶硅。本发明的实施例包括SRAM，双极晶体管，SOI横向二极管，MOSFET和SiGe晶体管。

2. 发明申请

US20120076172A1 MICRO-ELECTRO-MECHANICAL-SYSTEM TEMPERATURE SENSOR 失效
标题翻译：微电子机械系统温度传感器
公开(公告)号：US20120076172A1
公开(公告)日：2012-03-29
申请号：US12892406
申请日：2010-09-28
申请人： Jason P. Gill , David L. Harmon , Timothy D. Sullivan
发明人： Jason P. Gill , David L. Harmon , Timothy D. Sullivan
IPC分类号： G01K5/52
CPC分类号： G01K5/52
摘要： The present invention provides a micro-electro-mechanical-system (MEMS) temperature sensor that employs a suspended spiral comprising a material with a positive coefficient of thermal expansion. The thermal expansion of the suspended spiral is guided to by a set of guideposts to provide a linear movement of the free end of the suspended spiral, which is converted to an electrical signal by a set of conductive rotor azimuthal fins that are interdigitated with a set of conductive stator azimuthal fins by measuring the amount of capacitive coupling therebetween. Real time temperature may thus be measured through the in-situ measurement of the capacitive coupling. Optionally, the MEMS temperature sensor may have a ratchet and a pawl to enable ex-situ measurement.
摘要翻译：本发明提供了一种微电子机械系统（MEMS）温度传感器，其采用悬浮螺旋，其包括具有正的热膨胀系数的材料。悬挂螺旋的热膨胀由一组导轨引导以提供悬挂螺旋的自由端的线性运动，其被一组导电转子方位角翅片转换成电信号，所述导电转子方位角翅片与组相互指向通过测量导电定子方位翅片之间的电容耦合量。因此可以通过电容耦合的原位测量来测量实时温度。可选地，MEMS温度传感器可以具有棘轮和棘爪以使得能够进行非原位测量。

3. 发明授权

US07500208B2 Non-destructive evaluation of microstructure and interface roughness of electrically conducting lines in semiconductor integrated circuits in deep sub-micron regime 有权
标题翻译：在深亚微米体系的半导体集成电路中的导电线的微结构和界面粗糙度的非破坏性评估
公开(公告)号：US07500208B2
公开(公告)日：2009-03-03
申请号：US11673369
申请日：2007-02-09
申请人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
IPC分类号： G06F17/50 , G01R31/26
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.
摘要翻译：用于评估半导体集成电路中的线路的新型结构和方法。在每个包括多个线段的晶片上形成第一组多条线。所有线段长度相同。测量线路段的电阻。然后，基于所有部分的电阻来确定第一行几何调整。第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。相同长度和厚度的第二组多条线可以形成在同一晶片上。然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

4. 发明授权

US07639032B2 Structure for monitoring stress-induced degradation of conductive interconnects 失效
标题翻译：用于监测导电互连的应力导致退化的结构
公开(公告)号：US07639032B2
公开(公告)日：2009-12-29
申请号：US12004011
申请日：2007-12-19
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

5. 发明申请

US20100021656A1 LOW LEAKAGE METAL-CONTAINING CAP PROCESS USING OXIDATION 有权
标题翻译：使用氧化的低泄漏金属包覆工艺
公开(公告)号：US20100021656A1
公开(公告)日：2010-01-28
申请号：US12573407
申请日：2009-10-05
申请人： Jeffrey P. Gambino , Jason P. Gill , Sean Smith , Jean E. Wynne
发明人： Jeffrey P. Gambino , Jason P. Gill , Sean Smith , Jean E. Wynne
IPC分类号： C23C26/00 , B05D5/12
CPC分类号： H01L23/53238 , H01L21/288 , H01L21/76829 , H01L21/76849 , H01L21/76856 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure which includes a metal-containing cap located atop each conductive feature that is present within a dielectric material is provided in which a surface region of the metal-containing cap is oxidized prior to the subsequent deposition of any other dielectric material thereon. Moreover, metal particles that are located on the surface of the dielectric material between the conductive features are also oxidized at the same time as the surface region of the metal-containing cap. This provides a structure having a reduced leakage current. In accordance with the present invention, the oxidation step is performed after electroless plating of the metal-containing cap and prior to the deposition of a dielectric capping layer or an overlying interlayer or intralevel dielectric material.
摘要翻译：提供一种互连结构，其包括位于电介质材料内部的每个导电特征顶部的位于金属的盖的顶盖，其中含金属盖的表面区域在其后沉积任何其它电介质材料之前被氧化。此外，位于介电材料表面之间的导电特征之间的金属颗粒也与含金属盖的表面区域同时被氧化。这提供了具有减小的漏电流的结构。根据本发明，氧化步骤是在含金属盖的无电镀之后并且在沉积介电覆盖层或上覆的中间层或电介质材料之前进行的。

6. 发明授权

US07511378B2 Enhancement of performance of a conductive wire in a multilayered substrate 失效
标题翻译：提高多层基板中的导线的性能
公开(公告)号：US07511378B2
公开(公告)日：2009-03-31
申请号：US11442911
申请日：2006-05-30
申请人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
发明人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
IPC分类号： H01L23/48
CPC分类号： G06F17/5077 , H01L23/3677 , H01L23/522 , H01L23/5226 , H01L2924/0002 , H05K1/0201 , H05K3/0005 , H01L2924/00
摘要： An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.
摘要翻译：具有布线的电子结构以及用于限制布线中的温度梯度的结构设计的相关方法。该电子结构包括具有包括不物理接触的第一和第二线的层的衬底。由于焦耳加热相对于第一和第二导线中的电流密度，第一和第二导线适于处于升高的温度。第一导线通过存在于层之外的导电和导热结构电耦合到第二导线。第二导线的宽度被调整为将第一导线中的温度梯度限制在低于预定足够小的阈值，以便基本上减轻第一线中的电迁移的不利影响。

7. 发明申请

US20080231312A1 Structure for modeling stress-induced degradation of conductive interconnects 失效
标题翻译：用于建模导电互连的应力诱导退化的结构
公开(公告)号：US20080231312A1
公开(公告)日：2008-09-25
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译：提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平延伸平面该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。下导电或半导体元件可以与下通孔的底端接触。上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

8. 发明授权

US07867897B2 Low leakage metal-containing cap process using oxidation 有权
标题翻译：低泄漏含金属帽工艺使用氧化
公开(公告)号：US07867897B2
公开(公告)日：2011-01-11
申请号：US12573407
申请日：2009-10-05
申请人： Jeffrey P. Gambino , Jason P. Gill , Sean Smith , Jean E. Wynne
发明人： Jeffrey P. Gambino , Jason P. Gill , Sean Smith , Jean E. Wynne
IPC分类号： H01L21/44
CPC分类号： H01L23/53238 , H01L21/288 , H01L21/76829 , H01L21/76849 , H01L21/76856 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure which includes a metal-containing cap located atop each conductive feature that is present within a dielectric material is provided in which a surface region of the metal-containing cap is oxidized prior to the subsequent deposition of any other dielectric material thereon. Moreover, metal particles that are located on the surface of the dielectric material between the conductive features are also oxidized at the same time as the surface region of the metal-containing cap. This provides a structure having a reduced leakage current. In accordance with the present invention, the oxidation step is performed after electroless plating of the metal-containing cap and prior to the deposition of a dielectric capping layer or an overlying interlayer or intralevel dielectric material.
摘要翻译：提供一种互连结构，其包括位于电介质材料内部的每个导电特征顶部的位于金属的盖的顶盖，其中含金属盖的表面区域在其后沉积任何其它电介质材料之前被氧化。此外，位于介电材料表面之间的导电特征之间的金属颗粒也与含金属盖的表面区域同时被氧化。这提供了具有减小的漏电流的结构。根据本发明，氧化步骤是在含金属盖的无电镀之后并且在沉积介电覆盖层或上覆的中间层或电介质材料之前进行的。

9. 发明授权

US07830019B2 Via bottom contact and method of manufacturing same 有权
标题翻译：通过底部接触及其制造方法
公开(公告)号：US07830019B2
公开(公告)日：2010-11-09
申请号：US12431289
申请日：2009-04-28
申请人： Kaushik Chanda , Lawrence A. Clevenger , Andrew P. Cowley , Jason P. Gill , Baozhen Li , Chih-Chao Yang
发明人： Kaushik Chanda , Lawrence A. Clevenger , Andrew P. Cowley , Jason P. Gill , Baozhen Li , Chih-Chao Yang
IPC分类号： H01L23/04
CPC分类号： H01L21/76865 , H01L21/76805 , H01L21/76846 , H01L21/76886
摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.
摘要翻译：制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。该方法产生防止开路的结构。

10. 发明申请

US20090200673A1 VIA BOTTOM CONTACT AND METHOD OF MANUFACTURING SAME 有权
标题翻译：通过底部接触及其制造方法
公开(公告)号：US20090200673A1
公开(公告)日：2009-08-13
申请号：US12431289
申请日：2009-04-28
申请人： Kaushik Chanda , Lawrence A. Clevenger , Andrew P. Cowley , Jason P. Gill , Baozhen Li , Chih-Chao Yang
发明人： Kaushik Chanda , Lawrence A. Clevenger , Andrew P. Cowley , Jason P. Gill , Baozhen Li , Chih-Chao Yang
IPC分类号： H01L23/532 , H01L23/48
CPC分类号： H01L21/76865 , H01L21/76805 , H01L21/76846 , H01L21/76886
摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.
摘要翻译：制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。该方法产生防止开路的结构。

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