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1. 发明授权

US06291342B1 Methods of forming titanium nitride composite layers using composite gases having increasing TiCl4 to NH3 ratios 有权
公开(公告)号：US06291342B1
公开(公告)日：2001-09-18
申请号：US09767523
申请日：2001-01-23
申请人： Jang-eun Lee , Ju-hyuck Chung , Tae-wook Seo
发明人： Jang-eun Lee , Ju-hyuck Chung , Tae-wook Seo
IPC分类号： H01L214763
摘要： A method of forming a multilayer titanium nitride film hardly containing any Cl component by a multiple step chemical vapor deposition method, and a method of manufacturing a semiconductor device using the same are provided. In the present invention, a multilayer TiN film is formed by multiple step chemical vapor deposition (CVD) on a semiconductor substrate on which an underlayer is formed. In order to form the multilayer TiN film, an underlayer protective TiN film is formed by forming a first TiN film on the underlayer and NH3 annealing the first TiN film. A main TiN film is formed by forming a second TiN film on the underlayer protective TiN film and NH3 annealing the second TiN film. A source gas used in order to form the first TiN film has a smaller TiCl4 to NH3 gas flow ratio than a source gas for forming the second TiN film. In order to apply the multilayer TiN film to the fabrication of the semiconductor device, an insulating film having a contact hole is formed on a semiconductor substrate. A Ti film is formed on the inner wall of the contact hole. A multilayer TiN film is formed on the Ti film by the multiple step CVD method. A metal plug is formed on the multilayer TiN film.

2. 发明授权

US06207557B1 Method of forming multilayer titanium nitride film by multiple step chemical vapor deposition process and method of manufacturing semiconductor device using the same 有权
标题翻译：通过多步化学气相沉积工艺形成多层氮化钛膜的方法和使用其制造半导体器件的方法
公开(公告)号：US06207557B1
公开(公告)日：2001-03-27
申请号：US09356928
申请日：1999-07-19
申请人： Jang-eun Lee , Ju-hyuck Chung , Tae-wook Seo
发明人： Jang-eun Lee , Ju-hyuck Chung , Tae-wook Seo
IPC分类号： H01L214763
CPC分类号： H01L21/76856 , H01L21/28556 , H01L21/76843 , H01L21/76846
摘要： A method of forming a multilayer titanium nitride film hardly containing any Cl component by a multiple step chemical vapor deposition method, and a method of manufacturing a semiconductor device using the same are provided. In the present invention, a multilayer TiN film is formed by multiple step chemical vapor deposition (CVD) on a semiconductor substrate on which an underlayer is formed. In order to form the multilayer TiN film, an underlayer protective TiN film is formed by forming a first TiN film on the underlayer and NH3 annealing the first TiN film. A main TiN film is formed by forming a second TiN film on the underlayer protective TiN film and NH3 annealing the second TiN film. A source gas used in order to form the first TiN film has a smaller TiCl4 to NH3 gas flow ratio than a source gas for forming the second TiN film. In order to apply the multilayer TiN film to the fabrication of the semiconductor device, an insulating film having a contact hole is formed on a semiconductor substrate. A Ti film is formed on the inner wall of the contact hole. A multilayer TiN film is formed on the Ti film by the multiple step CVD method. A metal plug is formed on the multilayer TiN film.
摘要翻译：提供了通过多步化学气相沉积法形成几乎不含任何Cl成分的多层氮化钛膜的方法，以及制造使用其的半导体器件的方法。在本发明中，通过在其上形成有底层的半导体衬底上进行多步化学气相沉积（CVD）形成多层TiN膜。为了形成多层TiN膜，通过在底层上形成第一TiN膜，并对第一TiN膜进行NH 3退火，形成下层保护TiN膜。通过在底层保护性TiN膜上形成第二TiN膜并使NH 3退火第二TiN膜来形成主TiN膜。用于形成第一TiN膜的源气体与用于形成第二TiN膜的源气体相比具有较小的TiCl 4与NH 3气体流量比。为了将多层TiN膜施加到半导体器件的制造中，在半导体衬底上形成具有接触孔的绝缘膜。在接触孔的内壁上形成有Ti膜。通过多步CVD法在Ti膜上形成多层TiN膜。在多层TiN膜上形成金属塞。

3. 发明申请

US20060278341A1 Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates 审中-公开
公开(公告)号：US20060278341A1
公开(公告)日：2006-12-14
申请号：US11506833
申请日：2006-08-21
申请人： Jeong-hyuck Park , Hee-duk Kim , Jung-hun Cho , Jong-wook Choi , Sung-bum Cho , Young-koo Lee , Jin-sung Kim , Jang-eun Lee , Ju-hyuck Chung , Sun-hoo Park , Jae-hyun Lee , Shin-woo Nam
发明人： Jeong-hyuck Park , Hee-duk Kim , Jung-hun Cho , Jong-wook Choi , Sung-bum Cho , Young-koo Lee , Jin-sung Kim , Jang-eun Lee , Ju-hyuck Chung , Sun-hoo Park , Jae-hyun Lee , Shin-woo Nam
IPC分类号： H01L21/306
CPC分类号： H01J37/32431 , C23C16/4583 , C23C16/4585 , C23C16/54 , H01J37/32623 , H01J37/32642 , H01L21/32136 , H01L21/6831 , H01L21/68735 , Y10T117/10
摘要： A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

4. 发明授权

US06797109B2 Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates 失效
标题翻译：用于制造半导体器件的处理室，能够减少微粒污染
公开(公告)号：US06797109B2
公开(公告)日：2004-09-28
申请号：US10235976
申请日：2002-09-06
申请人： Jeong-hyuck Park , Hee-duk Kim , Jung-hun Cho , Jong-wook Choi , Sung-bum Cho , Young-koo Lee , Jin-sung Kim , Jang-eun Lee , Ju-hyuck Chung , Sun-hoo Park , Jae-hyun Lee , Shin-woo Nam
发明人： Jeong-hyuck Park , Hee-duk Kim , Jung-hun Cho , Jong-wook Choi , Sung-bum Cho , Young-koo Lee , Jin-sung Kim , Jang-eun Lee , Ju-hyuck Chung , Sun-hoo Park , Jae-hyun Lee , Shin-woo Nam
IPC分类号： H05H100
CPC分类号： H01J37/32431 , C23C16/4583 , C23C16/4585 , C23C16/54 , H01J37/32623 , H01J37/32642 , H01L21/32136 , H01L21/6831 , H01L21/68735 , Y10T117/10
摘要： A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.
摘要翻译：用于制造用于蚀刻半导体晶片上的材料层的半导体器件的处理室包括用于保持半导体晶片的静电卡盘和围绕静电卡盘上的半导体晶片侧的环形边缘环，以防止半导体晶片从其原始位置脱离。环形边缘环具有面向半导体晶片的侧面并与半导体晶片的侧面牢固接触的第一侧。

5. 发明授权

US06464794B1 Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates 失效
标题翻译：用于制造半导体器件的处理室，能够减少微粒污染
公开(公告)号：US06464794B1
公开(公告)日：2002-10-15
申请号：US09404631
申请日：1999-09-23
申请人： Jeong-hyuck Park , Hee-duk Kim , Jung-hun Cho , Jong-wook Choi , Sung-bum Cho , Young-koo Lee , Jin-sung Kim , Jang-eun Lee , Ju-hyuck Chung , Sun-hoo Park , Jae-hyun Lee , Shin-woo Nam
发明人： Jeong-hyuck Park , Hee-duk Kim , Jung-hun Cho , Jong-wook Choi , Sung-bum Cho , Young-koo Lee , Jin-sung Kim , Jang-eun Lee , Ju-hyuck Chung , Sun-hoo Park , Jae-hyun Lee , Shin-woo Nam
IPC分类号： C23C1600
CPC分类号： H01J37/32431 , C23C16/4583 , C23C16/4585 , C23C16/54 , H01J37/32623 , H01J37/32642 , H01L21/32136 , H01L21/6831 , H01L21/68735 , Y10T117/10
摘要： A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.
摘要翻译：用于制造用于蚀刻半导体晶片上的材料层的半导体器件的处理室包括用于保持半导体晶片的静电卡盘和围绕静电卡盘上的半导体晶片侧的环形边缘环，以防止半导体晶片从其原始位置脱离。环形边缘环具有面向半导体晶片的侧面并与半导体晶片的侧面牢固接触的第一侧。

6. 发明授权

US07645695B2 Method of manufacturing a semiconductor element 失效
标题翻译：制造半导体元件的方法
公开(公告)号：US07645695B2
公开(公告)日：2010-01-12
申请号：US11730665
申请日：2007-04-03
申请人： Jun-hwan Oh , Hong-seong Son , Sang-min Lee , Ju-hyuck Chung
发明人： Jun-hwan Oh , Hong-seong Son , Sang-min Lee , Ju-hyuck Chung
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/02063 , Y10S438/906
摘要： A method of manufacturing a semiconductor element, includes forming a lower metal wiring layer and an interlayer insulating film on a substrate, forming an opening through the interlayer insulating film, such that the opening is in communication with an upper surface of the lower metal wiring layer, cleaning the opening, forming a metal wiring line protecting film in the opening, such that the metal wiring line protecting film covers the lower metal wiring layer, washing the opening to remove the metal wiring line protecting film, such that a top surface of the lower metal wiring layer is exposed, and drying the substrate.
摘要翻译：一种半导体元件的制造方法，其特征在于，在基板上形成下部金属布线层和层间绝缘膜，通过所述层间绝缘膜形成开口，使得所述开口与所述下部金属布线层的上表面连通，清洗开口，在开口中形成金属布线保护膜，使得金属布线保护膜覆盖下金属布线层，清洗开口以除去金属布线保护膜，使得金属布线保护膜的顶表面下金属布线层露出，干燥基板。

7. 发明申请

US20060024948A1 Method of fabricating dual damascene interconnection 有权
标题翻译：双镶嵌互连方法
公开(公告)号：US20060024948A1
公开(公告)日：2006-02-02
申请号：US11157363
申请日：2005-06-21
申请人： Hyeok-sang Oh , Ju-hyuck Chung , Il-goo Kim
发明人： Hyeok-sang Oh , Ju-hyuck Chung , Il-goo Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807
摘要： In a method of fabricating a dual damascene interconnection, a reliable trench profile is secured. The method includes forming a lower interconnect feature on a substrate, forming a dielectric layer on the lower interconnect feature, forming a hard mask on the dielectric layer, forming a via in the dielectric layer using the hard mask as an etch mask, forming a trench hard mask defining a trench by patterning the hard mask, forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask, removing the trench hard mask using wet etch, and forming an upper interconnection line by filling the trench and the via with an interconnection material.
摘要翻译：在制造双镶嵌互连的方法中，确保可靠的沟槽轮廓。该方法包括在衬底上形成下部互连特征，在下互连特征上形成电介质层，在电介质层上形成硬掩模，使用硬掩模作为蚀刻掩模在电介质层中形成通孔，形成沟槽硬掩模通过图案化硬掩模来形成沟槽，通过使用沟槽硬掩模作为蚀刻掩模部分地蚀刻介电层，形成与通孔连接并且其中形成上互连线的沟槽，去除沟槽硬掩模，并且通过用互连材料填充沟槽和通孔来形成上互连线。

8. 发明申请

US20070232064A1 Method of manufacturing a semiconductor element 失效
标题翻译：制造半导体元件的方法
公开(公告)号：US20070232064A1
公开(公告)日：2007-10-04
申请号：US11730665
申请日：2007-04-03
申请人： Jun-hwan Oh , Hong-seong Son , Sang-min Lee , Ju-hyuck Chung
发明人： Jun-hwan Oh , Hong-seong Son , Sang-min Lee , Ju-hyuck Chung
IPC分类号： H01L21/44
CPC分类号： H01L21/76814 , H01L21/02063 , Y10S438/906
摘要： A method of manufacturing a semiconductor element, includes forming a lower metal wiring layer and an interlayer insulating film on a substrate, forming an opening through the interlayer insulating film, such that the opening is in communication with an upper surface of the lower metal wiring layer, cleaning the opening, forming a metal wiring line protecting film in the opening, such that the metal wiring line protecting film covers the lower metal wiring layer, washing the opening to remove the metal wiring line protecting film, such that a top surface of the lower metal wiring layer is exposed, and drying the substrate.
摘要翻译：一种半导体元件的制造方法，其特征在于，在基板上形成下部金属布线层和层间绝缘膜，通过所述层间绝缘膜形成开口，使得所述开口与所述下部金属布线层的上表面连通，清洗开口，在开口中形成金属布线保护膜，使得金属布线保护膜覆盖下金属布线层，清洗开口以除去金属布线保护膜，使得金属布线保护膜的顶表面下金属布线层露出，干燥基板。

9. 发明申请

US20060024941A1 Method of forming metal interconnect of semiconductor device 审中-公开
标题翻译：形成半导体器件金属互连的方法
公开(公告)号：US20060024941A1
公开(公告)日：2006-02-02
申请号：US11191518
申请日：2005-07-28
申请人： Jeong-hoon Son , Hyeok-sang Oh , Seong-il Kim , Ju-hyuck Chung
发明人： Jeong-hoon Son , Hyeok-sang Oh , Seong-il Kim , Ju-hyuck Chung
IPC分类号： H01L21/44
CPC分类号： H01L21/76862 , H01L21/76808 , H01L21/76831 , H01L21/76844 , H01L21/76846
摘要： In a method of forming a metal interconnect of a semiconductor device using a damascene process, an etch stop layer and an insulating layer are successively formed on a semiconductor substrate, into which a conductive pattern is filled. Next, the etch stop layer and the insulating layer are patterned so that an opening for exposing the etch stop layer is formed. Subsequently, a first diffusion barrier layer is formed along inner surfaces of the opening. The first diffusion barrier layer on a bottom surface of the opening and the etch stop layer are removed through an etch process using a sputtering method. Finally, a conductive material which is electrically connected to the conductive pattern is filled into the opening.
摘要翻译：在使用镶嵌工艺形成半导体器件的金属互连的方法中，在半导体衬底上依次形成蚀刻停止层和绝缘层，其中填充有导电图案。接下来，蚀刻停止层和绝缘层被图案化，从而形成用于暴露蚀刻停止层的开口。随后，沿开口的内表面形成第一扩散阻挡层。通过使用溅射法的蚀刻工艺去除开口的底表面上的第一扩散阻挡层和蚀刻停止层。最后，将与导电图案电连接的导电材料填充到开口中。

10. 发明授权

US07176126B2 Method of fabricating dual damascene interconnection 有权
标题翻译：双镶嵌互连方法
公开(公告)号：US07176126B2
公开(公告)日：2007-02-13
申请号：US11157363
申请日：2005-06-21
申请人： Hyeok-sang Oh , Ju-hyuck Chung , Il-goo Kim
发明人： Hyeok-sang Oh , Ju-hyuck Chung , Il-goo Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807
摘要： In a method of fabricating a dual damascene interconnection, a reliable trench profile is secured. The method includes forming a lower interconnect feature on a substrate, forming a dielectric layer on the lower interconnect feature, forming a hard mask on the dielectric layer, forming a via in the dielectric layer using the hard mask as an etch mask, forming a trench hard mask defining a trench by patterning the hard mask, forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask, removing the trench hard mask using wet etch, and forming an upper interconnection line by filling the trench and the via with an interconnection material.
摘要翻译：在制造双镶嵌互连的方法中，确保可靠的沟槽轮廓。该方法包括在衬底上形成下部互连特征，在下互连特征上形成电介质层，在电介质层上形成硬掩模，使用硬掩模作为蚀刻掩模在电介质层中形成通孔，形成沟槽硬掩模通过图案化硬掩模来形成沟槽，通过使用沟槽硬掩模作为蚀刻掩模部分地蚀刻介电层，形成与通孔连接并且其中形成上互连线的沟槽，去除沟槽硬掩模，并且通过用互连材料填充沟槽和通孔来形成上互连线。

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