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1. 发明申请

US20070171732A1 ORGANIC MEMORY 有权
标题翻译：有机记忆
公开(公告)号：US20070171732A1
公开(公告)日：2007-07-26
申请号：US11309037
申请日：2006-06-12
申请人： Jan-Ruei Lin , Shyh-Shyuan Sheu , Wei-Jen Chang
发明人： Jan-Ruei Lin , Shyh-Shyuan Sheu , Wei-Jen Chang
IPC分类号： G11C7/10 , G11C11/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C2213/79
摘要： An organic memory is provided. The organic memory at least comprises a plurality of select lines, a plurality of data lines, a bit cell array, and a plurality of digital sensing circuits. The bit cell array comprises a plurality of bit cells, wherein each bit cell comprises an organic memory cell and a switch element. Each digital sensing circuit comprises a current-to-voltage converter and a sensing block circuit. Therefore, the present invention provides a complete digital sensing mechanism of an organic memory IC, which is practicable and suitable for mass-production.
摘要翻译：提供有机存储器。有机存储器至少包括多条选择线，多条数据线，位单元阵列和多个数字感测电路。位单元阵列包括多个位单元，其中每个位单元包括有机存储单元和开关元件。每个数字感测电路包括电流 - 电压转换器和感测块电路。因此，本发明提供了一种有机存储器IC的完整数字感测机构，其可行且适用于批量生产。

2. 发明授权

US07236390B1 Bit cell of organic memory 有权
标题翻译：有机存储器的位单元
公开(公告)号：US07236390B1
公开(公告)日：2007-06-26
申请号：US11308146
申请日：2006-03-08
申请人： Wei-Jen Chang , Shyh-Shyuan Sheu , Jan-Ruei Lin
发明人： Wei-Jen Chang , Shyh-Shyuan Sheu , Jan-Ruei Lin
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/00 , B82Y10/00 , G11C13/0014 , G11C13/0028 , G11C2213/79
摘要： A bit cell of an organic memory is provided. The bit cell of the organic memory comprises an organic memory cell, a first transistor, a current mirror and a second transistor. To connect the organic memory cell to a data line, the first transistor is activated for reading and the second transistor is activated for writing. Furthermore, the first transistor has a greater size than the second transistor. Therefore, a fast processing time in writing and a large conduction current in reading are catered for. In addition, the current mirror amplifies the conduction current in reading and increases the capacity for resisting the interference by adjacent bit cell.
摘要翻译：提供有机存储器的位单元。有机存储器的位单元包括有机存储单元，第一晶体管，电流镜和第二晶体管。为了将有机存储单元连接到数据线，第一晶体管被激活用于读取，第二晶体管被激活用于写入。此外，第一晶体管具有比第二晶体管更大的尺寸。因此，在写入时的快速处理时间和读取中的大的传导电流被满足。此外，电流镜放大读取中的导通电流，并增加抵抗相邻位单元的干扰的能力。

3. 发明申请

US20070153562A1 BIT CELL OF ORGANIC MEMORY 有权
标题翻译：有机存储器的单元格
公开(公告)号：US20070153562A1
公开(公告)日：2007-07-05
申请号：US11308146
申请日：2006-03-08
申请人： Wei-Jen Chang , Shyh-Shyuan Sheu , Jan-Ruei Lin
发明人： Wei-Jen Chang , Shyh-Shyuan Sheu , Jan-Ruei Lin
IPC分类号： H01L29/08 , H01L35/24 , G11C11/00 , G11C13/00 , H01L51/00
CPC分类号： G11C13/00 , B82Y10/00 , G11C13/0014 , G11C13/0028 , G11C2213/79
摘要： A bit cell of an organic memory is provided. The bit cell of the organic memory comprises an organic memory cell, a first transistor, a current mirror and a second transistor. To connect the organic memory cell to a data line, the first transistor is activated for reading and the second transistor is activated for writing. Furthermore, the first transistor has a greater size than the second transistor. Therefore, a fast processing time in writing and a large conduction current in reading are catered for. In addition, the current mirror amplifies the conduction current in reading and increases the capacity for resisting the interference by adjacent bit cell.
摘要翻译：提供有机存储器的位单元。有机存储器的位单元包括有机存储单元，第一晶体管，电流镜和第二晶体管。为了将有机存储单元连接到数据线，第一晶体管被激活用于读取，第二晶体管被激活用于写入。此外，第一晶体管具有比第二晶体管更大的尺寸。因此，在写入时的快速处理时间和读取中的大的传导电流被满足。此外，电流镜放大读取中的导通电流，并增加抵抗相邻位单元的干扰的能力。

4. 发明授权

US07515490B2 Sensing circuit for organic memory 有权
标题翻译：有机记忆传感电路
公开(公告)号：US07515490B2
公开(公告)日：2009-04-07
申请号：US11309037
申请日：2006-06-12
申请人： Jan-Ruei Lin , Shyh-Shyuan Sheu , Wei-Jen Chang
发明人： Jan-Ruei Lin , Shyh-Shyuan Sheu , Wei-Jen Chang
IPC分类号： G11C7/06 , G11C7/10 , G11C7/08 , G11C11/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C2213/79
摘要： An organic memory at least includes a number of select lines, a number of data lines, a bit cell array, and a number of digital sensing circuits. The bit cell array includes a number of bit cells, wherein each bit cell includes an organic memory cell and a switch element. Each digital sensing circuit includes a current-to-voltage converter and a sensing block circuit. Therefore, a complete digital sensing mechanism of an organic memory IC is formed and is practicable and suitable for mass-production.
摘要翻译：有机存储器至少包括多条选择线，多条数据线，位单元阵列和多个数字感测电路。位单元阵列包括多个位单元，其中每个位单元包括有机存储单元和开关元件。每个数字感测电路包括电流 - 电压转换器和感测块电路。因此，形成有机存储器IC的完整的数字感测机构，并且是可行的并且适合于批量生产。

5. 发明授权

US07242174B1 Digital sensing circuit 有权
标题翻译：数字感应电路
公开(公告)号：US07242174B1
公开(公告)日：2007-07-10
申请号：US11309002
申请日：2006-06-07
申请人： Shyh-Shyuan Sheu , Wei-Jen Chang , Jan-Ruei Lin
发明人： Shyh-Shyuan Sheu , Wei-Jen Chang , Jan-Ruei Lin
IPC分类号： G01R19/00 , G11C7/00
CPC分类号： G11C7/067 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C27/02
摘要： A digital sensing circuit capable of sensing bit information stored in a bit cell of an organic memory is provided. The digital sensing circuit includes a current-to-voltage converter, a reset block circuit, and a sensing block circuit. The current-to-voltage converter converts a conduction current into a voltage signal. The sensing block circuit buffers and outputs the bit information according to the voltage signal. Therefore, the challenge of design and layout of the present invention is very low so that the yield rate will be improved. Hence, a practical memory device suitable for mass-production is achieved.
摘要翻译：提供一种能够感测存储在有机存储器的位单元中的位信息的数字感测电路。数字感测电路包括电流 - 电压转换器，复位块电路和感测块电路。电流 - 电压转换器将传导电流转换为电压信号。感测块电路根据电压信号缓冲并输出位信息。因此，本发明的设计和布局的挑战非常低，从而提高了成品率。因此，实现了适合于批量生产的实用的记忆装置。

6. 发明申请

US20070152650A1 DIGITAL SENSING CIRCUIT 有权
标题翻译：数字感应电路
公开(公告)号：US20070152650A1
公开(公告)日：2007-07-05
申请号：US11309002
申请日：2006-06-07
申请人： Shyh-Shyuan Sheu , Wei-Jen Chang , Jan-Ruei Lin
发明人： Shyh-Shyuan Sheu , Wei-Jen Chang , Jan-Ruei Lin
IPC分类号： G01R19/00
CPC分类号： G11C7/067 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C27/02
摘要： A digital sensing circuit capable of sensing bit information stored in a bit cell of an organic memory is provided. The digital sensing circuit comprises a current-to-voltage converter, a reset block circuit, and a sensing block circuit. The current-to-voltage converter converts a conduction current into a voltage signal. The sensing block circuit buffers and outputs the bit information according to the voltage signal. Therefore, the challenge of design and layout of the present invention is very low so that the yield rate will be improved. Hence, a practical memory device suitable for mass-production is achieved.
摘要翻译：提供一种能够感测存储在有机存储器的位单元中的位信息的数字感测电路。数字感测电路包括电流 - 电压转换器，复位块电路和感测块电路。电流 - 电压转换器将传导电流转换为电压信号。感测块电路根据电压信号缓冲并输出位信息。因此，本发明的设计和布局的挑战非常低，从而提高了成品率。因此，实现了适合于批量生产的实用的记忆装置。

7. 发明申请

US20070103962A1 Programmable memory cell and operation method 失效
标题翻译：可编程存储单元和操作方法
公开(公告)号：US20070103962A1
公开(公告)日：2007-05-10
申请号：US11271550
申请日：2005-11-09
申请人： Keng-Li Su , Shyh-Shyuan Sheu , Jan-Ruei Lin , Wei-Jen Chang , Chen-Pang Kung
发明人： Keng-Li Su , Shyh-Shyuan Sheu , Jan-Ruei Lin , Wei-Jen Chang , Chen-Pang Kung
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , B82Y10/00 , G11C13/0014 , G11C2213/79
摘要： A memory array including a plurality of programmable memory cells, a plurality of column lines and a plurality of row lines is introduced. Each of the programmable memory cells is coupled to corresponding one of the column lines and corresponding one of the row lines. Each of the programmable memory cells includes an organic memory cell and an active switching element. The active switching element is controlled by the column line and interposed between the row line and the organic memory cell. Under controlling of the column line, the active switching element is turned on to coupling the row line and the organic memory cell to connect to each other.
摘要翻译：引入包括多个可编程存储器单元，多个列线和多个行线的存储器阵列。每个可编程存储器单元耦合到对应的列线和对应的一行行。每个可编程存储器单元包括有机存储单元和有源开关元件。有源开关元件由列线控制并插入在行线和有机存储单元之间。在列线的控制下，有源开关元件被接通以将行线和有机存储器单元耦合以彼此连接。

8. 发明申请

US20060055687A1 Brightness control circuits 审中-公开
标题翻译：亮度控制电路
公开(公告)号：US20060055687A1
公开(公告)日：2006-03-16
申请号：US11056173
申请日：2005-02-14
申请人： Shyh-Shyuan Sheu , Lieh-Chiu Lin , Ming-Daw Chen , Jan-Ruei Lin
发明人： Shyh-Shyuan Sheu , Lieh-Chiu Lin , Ming-Daw Chen , Jan-Ruei Lin
IPC分类号： G09G5/00
CPC分类号： G09G3/2014 , G09G2310/027 , H03M1/84
摘要： Brightness control circuits and drivers and display devices using the same. In the brightness control circuit, a current digital-to-analog converter (DAC) receives a digital code and generates a control current, and an one-shot circuit is coupled to the current DAC to generate a pulse width modulated (PWM) signal according to the control current and a clock signal. The digital code and pulse width modulated signal have an exponential relationship.
摘要翻译：亮度控制电路和驱动器及使用其的显示装置。在亮度控制电路中，电流数模转换器（DAC）接收数字代码并产生控制电流，并且单触发电路耦合到电流DAC以产生脉宽调制（PWM）信号，根据到控制电流和时钟信号。数字码和脉宽调制信号具有指数关系。

9. 发明授权

US07369424B2 Programmable memory cell and operation method 失效
标题翻译：可编程存储单元和操作方法
公开(公告)号：US07369424B2
公开(公告)日：2008-05-06
申请号：US11271550
申请日：2005-11-09
申请人： Keng-Li Su , Shyh-Shyuan Sheu , Jan-Ruel Lin , Wei-Jen Chang , Chen-Pang Kung
发明人： Keng-Li Su , Shyh-Shyuan Sheu , Jan-Ruel Lin , Wei-Jen Chang , Chen-Pang Kung
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C13/00 , B82Y10/00 , G11C13/0014 , G11C2213/79
摘要： A memory array including a plurality of programmable memory cells, a plurality of column lines and a plurality of row lines is introduced. Each of the programmable memory cells is coupled to corresponding one of the column lines and corresponding one of the row lines. Each of the programmable memory cells includes an organic memory cell and an active switching element. The active switching element is controlled by the column line and interposed between the row line and the organic memory cell. Under controlling of the column line, the active switching element is turned on to coupling the row line and the organic memory cell to connect to each other.
摘要翻译：引入包括多个可编程存储器单元，多个列线和多个行线的存储器阵列。每个可编程存储器单元耦合到对应的列线和对应的一行行。每个可编程存储器单元包括有机存储单元和有源开关元件。有源开关元件由列线控制并插入在行线和有机存储单元之间。在列线的控制下，有源开关元件被接通以将行线和有机存储器单元耦合以彼此连接。

10. 发明申请

US20130114325A1 NON-VOLATILE RANDOM ACCESS MEMORY COUPLED TO A FIRST, SECOND AND THIRD VOLTAGE AND OPERATION METHOD THEREOF 有权
标题翻译：非易失性随机访问存储器与第一，第二和第三电压和操作方法相关联
公开(公告)号：US20130114325A1
公开(公告)日：2013-05-09
申请号：US13332402
申请日：2011-12-21
申请人： Chih-He Lin , Wen-Pin Lin , Pi-Feng Chiu , Shyh-Shyuan Sheu
发明人： Chih-He Lin , Wen-Pin Lin , Pi-Feng Chiu , Shyh-Shyuan Sheu
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C14/009
摘要： A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.
摘要翻译：提供了非易失性随机存取存储器（NV-RAM）及其操作方法。 NV-RAM包括锁存单元，开关和第一至第四非易失性存储元件。第一和第三非易失性存储元件的第一端分别耦合到第一电压和第二电压。第一非易失性存储元件的第二端子和第二非易失性存储器元件的第一端子耦合到锁存单元的第一端子。第三非易失性存储元件的第二端子和第四非易失性存储元件的第一端子耦合到锁存单元的第二端子。第二和第四非易失性存储元件的第二端子耦合到开关的第一端子。开关的第二端子耦合到第三电压。

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