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1. 发明授权

US5712635A Digital to analog conversion using nonuniform sample rates 失效
标题翻译：使用不均匀采样率进行数模转换
公开(公告)号：US5712635A
公开(公告)日：1998-01-27
申请号：US612944
申请日：1996-08-29
申请人： James Wilson , Ronald A. Cellini , James M. Sobol
发明人： James Wilson , Ronald A. Cellini , James M. Sobol
IPC分类号： H03M1/66 , H03H17/06 , H03L7/08 , H03L7/093 , H03L7/099 , H03M3/02 , H03M7/36
CPC分类号： H03H17/06 , H03H17/0614 , H03H17/0628 , H03L7/08 , H03L7/093 , H03L7/0992 , H03M3/372 , H03L2207/50 , H03M3/50
摘要： A method and apparatus for digital to analog conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques In one embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream. In another embodiment, the digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream and then decimated by a fixed ratio. The frequency signal selection number is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the clock rate of the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of the incoming digital data stream to the data rate of the n-th order m-bit sigma-delta modulator.
摘要翻译： PCT No.PCT / US94 / 10269 Sec。 371日期：1996年8月29日 102（e）日期1996年8月29日PCT 1994年9月13日PCT公布。公开号WO95 / 08221 日期1995年3月23日一种使用Σ-Δ调制数字样本之间的时间间隔进行数模转换的方法和装置。本发明的方法和装置提供了时基的Σ-Δ调制，使得由不均匀采样产生的误差是频率形状的区域（即，转移到较高频率），其中它们可以通过常规滤波技术在一个实施例中，数字数据以固定比例内插，然后在Σ-Δ调制频率选择信号的控制下抽取，该Σ-Δ调制频率选择信号平均表示输入数字数据流的数据速率。在另一个实施例中，数字数据在Σ-Δ调制频率选择信号的控制下进行内插，该Σ-Δ调制频率选择信号平均表示输入数字数据流的数据速率，然后以固定比率抽取。使用第n级m位Σ-Δ调制器来调制频率信号选择数。因此，数据因此在第n级m位Σ-Δ调制器的时钟速率下从内插/抽取处理中出现。该方法和装置将输入的数字数据流的数据速率转换为第n阶m位Σ-Δ调制器的数据速率。

2. 发明授权

US5619202A Variable sample rate ADC 失效
公开(公告)号：US5619202A
公开(公告)日：1997-04-08
申请号：US343713
申请日：1994-11-22
申请人： James Wilson , Ronald A. Cellini , James M. Sobol
发明人： James Wilson , Ronald A. Cellini , James M. Sobol
IPC分类号： H03M3/02 , H03M1/00
CPC分类号： H03M3/372 , H03M3/50
摘要： A method and apparatus for analog-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional digital filtering techniques. In one embodiment, a sigma-delta ADC receives an analog input signal and converts the analog input signal to digital samples at an oversampling rate. A decimator, coupled to the sigma-delta ADC, receives the digital samples and decimates the digital samples to produce the digital samples at a preselected output sample rate, less than the oversampling rate. An ADC sample rate control circuit, coupled to the ADC, receives a frequency select signal representing the preselected output sample rate, and produces a noise-shaped clock signal for controlling operation of the ADC at the oversampling rate. The control circuit includes a sigma-delta modulator for sigma-delta modulating the frequency select signal. A randomizer/suppressor circuit, under control of the output of the sigma-delta modulator, receives an input clock signal and adjusts the frequency of the clock signal to produce a noise-shaped clock signal for controlling the oversampling rate of the ADC.

3. 发明授权

US5963160A Analog to digital conversion using nonuniform sample rates 失效
标题翻译：使用不均匀采样率的模数转换
公开(公告)号：US5963160A
公开(公告)日：1999-10-05
申请号：US612942
申请日：1996-08-29
申请人： James Wilson , Ronald A. Cellini , James M. Sobol
发明人： James Wilson , Ronald A. Cellini , James M. Sobol
IPC分类号： H03M1/00 , H03H17/00 , H03H17/06 , H03L7/08 , H03L7/093 , H03L7/099 , H03M1/12 , H03M3/02 , H03M3/04 , H03M7/36 , H03M3/00
CPC分类号： H03H17/06 , H03H17/0614 , H03H17/0628 , H03L7/08 , H03L7/093 , H03L7/0992 , H03M3/498 , H03L2207/50
摘要： A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. In another embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the sample rate selected by the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of an incoming digital data stream from an ADC to the data rate determined by the n-th order m-bit sigma-delta modulator.
摘要翻译： PCT No.PCT / US94 / 10268 Sec。 371日期：1996年8月29日 102（e）日期1996年8月29日PCT 1994年9月13日PCT公布。出版物WO95 / 08220 PCT 日期1995年3月23日一种使用数字样本之间的时间间隔的Σ-Δ调制进行模数转换的方法和装置。本发明的方法和装置提供了时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的区域（即，转移到更高的频率），其中它们可以通过常规滤波技术去除。在一个实施例中，在Σ-Δ调制频率选择信号的控制下内插数字数据，该Δ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率，然后以固定比率被抽取。在另一个实施例中，数字数据以固定比例内插，然后在Σ-Δ调制频率选择信号的控制下被抽取，该Σ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率。使用第n级m位Σ-Δ调制器调制频率选择信号。数据因此从由第n级m比特Σ-Δ调制器选择的采样率的内插/抽取处理中出现。该方法和装置将来自ADC的输入数字数据流的数据速率转换为由第n位m位Σ-Δ调制器确定的数据速率。

4. 发明授权

US5600320A Variable sample rate DAC 失效
标题翻译：可变采样率DAC
公开(公告)号：US5600320A
公开(公告)日：1997-02-04
申请号：US467703
申请日：1995-06-06
申请人： James Wilson , Ronald A. Cellini , James M. Sobol
发明人： James Wilson , Ronald A. Cellini , James M. Sobol
IPC分类号： H03M3/04 , H03M1/66
CPC分类号： H03M3/372 , H03M3/50
摘要： A method and apparatus for digital-to-analog conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional filtering techniques. In one embodiment, an oversampling modulator receives digital input samples and, responsive to a noise-shaped clock signal, modulates the digital input samples to produce modulated samples at an oversampling rate. The oversampling rate preferably is equal to an oversampling ratio times a preselected input sample rate. A DAC, coupled to the modulator, converts the modulated samples to an analog signal. A modulator sample rate control circuit, coupled to the modulator, receives a frequency select signal representing the preselected input sample rate, and produces the noise-shaped clock signal for controlling operation of the modulator at the oversampling rate. The control circuit preferably includes a first sigma-delta modulator that sigma-delta modulates the frequency select signal. The oversampling modulator preferably includes a second sigma-delta modulator.
摘要翻译：提供了使用数字样本之间的时间间隔的Σ-Δ调制进行数模转换的方法和装置。所述方法和装置包括时基的Σ-Δ调制，使得由非均匀采样产生的误差被频率形成为通过常规滤波技术降低的高频区域。在一个实施例中，过采样调制器接收数字输入样本，并且响应于噪声形状的时钟信号，以过采样率调制数字输入样本以产生调制样本。过采样率优选地等于过采样比乘以预选输入采样率。耦合到调制器的DAC将调制的样本转换为模拟信号。耦合到调制器的调制器采样率控制电路接收表示预选输入采样率的频率选择信号，并产生用于以过采样速率控制调制器的操作的噪声形状的时钟信号。控制电路优选地包括Σ-Δ调制频率选择信号的第一Σ-Δ调制器。过采样调制器优选地包括第二Σ-Δ调制器。

5. 发明授权

US5512897A Variable sample rate DAC 失效
标题翻译：可变采样率DAC
公开(公告)号：US5512897A
公开(公告)日：1996-04-30
申请号：US404235
申请日：1995-03-15
申请人： James Wilson , Ronald A. Cellini , James M. Sobol
发明人： James Wilson , Ronald A. Cellini , James M. Sobol
IPC分类号： H03M3/04 , H03M1/66
CPC分类号： H03M3/372 , H03M3/50
摘要： A method and apparatus for digital-to-analog conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional filtering techniques. In one embodiment, an oversampling modulator receives digital input samples and, responsive to a noise-shaped clock signal, modulates the digital input samples to produce modulated samples at an oversampling rate. The oversampling rate preferably is equal to an oversampling ratio times a preselected input sample rate. A DAC, coupled to the modulator, converts the modulated samples to an analog signal. A modulator sample rate control circuit, coupled to the modulator, receives a frequency select signal representing the preselected input sample rate, and produces the noise-shaped clock signal for controlling operation of the modulator at the oversampling rate. The control circuit preferably includes a first sigma-delta modulator that sigma-delta modulates the frequency select signal. The oversampling modulator preferably includes a second sigma-delta modulator.
摘要翻译：提供了使用数字样本之间的时间间隔的Σ-Δ调制进行数模转换的方法和装置。所述方法和装置包括时基的Σ-Δ调制，使得由非均匀采样产生的误差被频率形成为通过常规滤波技术降低的高频区域。在一个实施例中，过采样调制器接收数字输入样本，并且响应于噪声形状的时钟信号，以过采样率调制数字输入样本以产生调制样本。过采样率优选地等于过采样比乘以预选输入采样率。耦合到调制器的DAC将调制的样本转换为模拟信号。耦合到调制器的调制器采样率控制电路接收表示预选输入采样率的频率选择信号，并产生用于以过采样速率控制调制器的操作的噪声形状的时钟信号。控制电路优选地包括Σ-Δ调制频率选择信号的第一Σ-Δ调制器。过采样调制器优选地包括第二Σ-Δ调制器。

6. 发明授权

US5625358A Digital phase-locked loop utilizing a high order sigma-delta modulator 失效
标题翻译：采用高阶Σ-Δ调制器的数字锁相环
公开(公告)号：US5625358A
公开(公告)日：1997-04-29
申请号：US403291
申请日：1995-03-14
申请人： James Wilson , Ronald A. Cellini
发明人： James Wilson , Ronald A. Cellini
IPC分类号： H03H17/06 , H03L7/08 , H03L7/093 , H03L7/099 , H03M1/12 , H03M3/02 , H03M7/36
CPC分类号： H03H17/0614 , H03H17/0657 , H03H17/0664 , H03L7/08 , H03L7/093 , H03L7/0992 , H03M7/3022 , H03L2207/50
摘要： A method and apparatus for phase locking to an input signal and outputting a sigma-delta modulated control signal. The method and apparatus of the present invention provide a sigma-delta modulated control signal which can be utilized by any one of a decimator for decimating a digital data at a first data rate to a digital data at a second data rate and an interpolator for interpolating a digital data at a first data rate to a digital data at a second data rate. The decimator and the interpolator can be utilized in any one of an analog-to-digital converter, a digital-to-analog converter and a digital-to-digital converter. In one embodiment, a period of the input signal is determined and fed to a phase-locked loop which includes a sigma-delta modulator for providing the sigma-delta modulated control signal. The phase-locked loop also includes a phase detector for determining a phase and a frequency-difference between the input signal and a conversion signal generated by the phase-locked loop. The method and apparatus thus locks to the phase and the frequency of the input signal and provide a phase-locked sigma-delta-modulated control signal.
摘要翻译：一种用于相位锁定到输入信号并输出Σ-Δ调制控制信号的方法和装置。本发明的方法和装置提供了一种Σ-Δ调制控制信号，其可由抽取器中的任何一个利用，以第一数据速率将数字数据以第二数据速率抽取数字数据，以及用于内插的内插器以第一数据速率将数字数据以第二数据速率传送到数字数据。抽头和内插器可用于模数转换器，数 - 模转换器和数 - 数转换器中的任何一个。在一个实施例中，确定输入信号的周期并将其馈送到锁相环，该锁相环包括用于提供Σ-Δ调制控制信号的Σ-Δ调制器。锁相环还包括用于确定输入信号和由锁相环产生的转换信号之间的相位和频差的相位检测器。因此，该方法和装置锁定到输入信号的相位和频率，并提供锁相Σ-Δ调制控制信号。

7. 发明授权

US5485152A Analog to digital conversion using non-uniform sample rates 失效
标题翻译：使用不均匀采样率的模数转换
公开(公告)号：US5485152A
公开(公告)日：1996-01-16
申请号：US328560
申请日：1994-10-25
申请人： James Wilson , Ronald A. Cellini , James M. Sobol
发明人： James Wilson , Ronald A. Cellini , James M. Sobol
IPC分类号： H03M1/00 , H03H17/00 , H03H17/06 , H03L7/08 , H03L7/093 , H03L7/099 , H03M1/12 , H03M3/02 , H03M3/04 , H03M7/36
CPC分类号： H03H17/06 , H03H17/0614 , H03H17/0628 , H03L7/08 , H03L7/093 , H03L7/0992 , H03M3/498 , H03L2207/50
摘要： A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by non-uniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the sample rate selected by the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of an incoming digital data stream from an ADC to the data rate determined by the n-th order m-bit sigma-delta modulator.
摘要翻译：一种使用数字样本之间的时间间隔的Σ-Δ调制进行模数转换的方法和装置。本发明的方法和装置提供了时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的区域（即，转移到更高的频率），其中它们可以通过常规滤波被去除技术在一个实施例中，在Σ-Δ调制频率选择信号的控制下内插数字数据，该Δ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率，然后以固定比率被抽取。使用第n级m位Σ-Δ调制器调制频率选择信号。数据因此从由第n级m比特Σ-Δ调制器选择的采样率的内插/抽取处理中出现。该方法和装置将来自ADC的输入数字数据流的数据速率转换为由第n位m位Σ-Δ调制器确定的数据速率。

8. 发明授权

US5625359A Variable sample rate ADC 失效
标题翻译：可变采样率ADC
公开(公告)号：US5625359A
公开(公告)日：1997-04-29
申请号：US466215
申请日：1995-06-06
申请人： James Wilson , Ronald A. Cellini , James M. Sobol
发明人： James Wilson , Ronald A. Cellini , James M. Sobol
IPC分类号： H03M3/02 , H03M1/00
CPC分类号： H03M3/372 , H03M3/50
摘要： A method and apparatus for analog-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional digital filtering techniques. In one embodiment, a sigma-delta ADC receives an analog input signal and converts the analog input signal to digital samples at an oversampling rate. A decimator, coupled to the sigma-delta ADC, receives the digital samples and decimates the digital samples to produce the digital samples at a preselected output sample rate, less than the oversampling rate. An ADC sample rate control circuit, coupled to the ADC, receives a frequency select signal representing the preselected output sample rate, and produces a noise-shaped clock signal for controlling operation of the ADC at the oversampling rate. The control circuit includes a sigma-delta modulator for sigma-delta modulating the frequency select signal. A randomizer/suppressor circuit, under control of the output of the sigma-delta modulator, receives an input clock signal and adjusts the frequency of the clock signal to produce a noise-shaped clock signal for controlling the oversampling rate of the ADC.
摘要翻译：提供了一种使用数字样本之间的时间间隔的Σ-Δ调制进行模数转换的方法和装置。该方法和装置包括时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的高频区域，它们被传统的数字滤波技术所减少。在一个实施例中，Σ-ΔADC接收模拟输入信号，并以过采样速率将模拟输入信号转换成数字采样。耦合到Σ-ΔADC的抽取器接收数字采样并抽取数字采样，以预选的输出采样率产生数字样本，小于过采样率。耦合到ADC的ADC采样率控制电路接收表示预选输出采样率的频率选择信号，并产生用于以过采样速率控制ADC的操作的噪声形状的时钟信号。控制电路包括用于Σ-Δ调制频率选择信号的Σ-Δ调制器。在Σ-Δ调制器的输出控制下的随机化/抑制电路接收输入时钟信号并调节时钟信号的频率，以产生用于控制ADC过采样速率的噪声形时钟信号。

9. 发明授权

US5528240A Digital phase-locked loop utilizing a high order sigma-delta modulator 失效
标题翻译：采用高阶Σ-Δ调制器的数字锁相环
公开(公告)号：US5528240A
公开(公告)日：1996-06-18
申请号：US475226
申请日：1995-06-07
申请人： James Wilson , Ronald A. Cellini
发明人： James Wilson , Ronald A. Cellini
IPC分类号： H03H17/06 , H03L7/08 , H03L7/093 , H03L7/099 , H03M1/12 , H03M3/02 , H03M7/36
CPC分类号： H03H17/0614 , H03H17/0657 , H03H17/0664 , H03L7/08 , H03L7/093 , H03L7/0992 , H03M7/3022 , H03L2207/50
摘要： A method and apparatus for phase locking to an input signal and outputting a sigma-delta modulated control signal. The method and apparatus of the present invention provide a sigma-delta modulated control signal which can be utilized by any one of a decimator for decimating a digital data at a first data rate to a digital data at a second data rate and an interpolator for interpolating a digital data at a first data rate to a digital data at a second data rate. The decimator and the interpolator can be utilized in any one of an analog-to-digital converter, a digital-to-analog converter and a digital-to-digital converter. In one embodiment, a period of the input signal is determined and fed to a phase-locked loop which includes a sigma-delta modulator for providing the sigma-delta modulated control signal. The phase-locked loop also includes a phase detector for determining a phase and a frequency-difference between the input signal and a conversion signal generated by the phase-locked loop. The method and apparatus thus locks to the phase and the frequency of the input signal and provide a phase-locked sigma-delta-modulated control signal.
摘要翻译：一种用于相位锁定到输入信号并输出Σ-Δ调制控制信号的方法和装置。本发明的方法和装置提供了一种Σ-Δ调制控制信号，其可由抽取器中的任何一个利用，以第一数据速率将数字数据以第二数据速率抽取数字数据，以及用于内插的内插器以第一数据速率将数字数据以第二数据速率传送到数字数据。抽头和内插器可用于模数转换器，数 - 模转换器和数 - 数转换器中的任何一个。在一个实施例中，确定输入信号的周期并将其馈送到锁相环，该锁相环包括用于提供Σ-Δ调制控制信号的Σ-Δ调制器。锁相环还包括用于确定输入信号和由锁相环产生的转换信号之间的相位和频差的相位检测器。因此，该方法和装置锁定到输入信号的相位和频率，并提供锁相Σ-Δ调制控制信号。

10. 发明授权

US5892468A Digital-to-digital conversion using nonuniform sample rates 失效
公开(公告)号：US5892468A
公开(公告)日：1999-04-06
申请号：US732421
申请日：1997-01-16
申请人： James Wilson , Ronald A. Cellini , James M. Sobol
发明人： James Wilson , Ronald A. Cellini , James M. Sobol
IPC分类号： H03H17/06 , H03L7/08 , H03L7/099 , H03M1/12 , H03M3/02 , H03M7/36 , H03M7/00
CPC分类号： H03H17/06 , H03H17/0614 , H03H17/0628 , H03L7/08 , H03L7/0992 , H03L2207/50
摘要： A method and apparatus for digital-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that noise produced by NONUNIFORM sampling are frequency-shaped to a region (i.e., shifted to higher frequencies where it can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated (16) by fixed ratio and then decimated (21) under control of a first sigma-delta modulated frequency selection signal (26) that represents, on average, the data rate of the incoming digital data stream. Thereafter, the digital data is interpolated (30) under control of a second sigma-delta modulated frequency selection signal (46) that represents, on average, the data rate of the digital data to be output by the converter and then decimated (40) by a fixed ratio. In another embodiment, the digital data is interpolated under control of a first sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream and then decimated by a fixed ratio. Thereafter, the digital data is interpolated by a fixed ratio and then decimated under control of a second sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The first and second frequency signal selection numbers are modulated using n-th order m-bit sigma-delta modulators. The method and apparatus converts the data rate of the incoming digital data stream to the data rate of the first n-th m-bit sigma-delta modulator and then converts the digital data stream from the first sigma-delta modulator (20) to an output data rate determined by the second n-th order m-bit sigma-delta modulator (32).

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