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1. 发明授权

US08554851B2 Apparatus, system, and methods for facilitating one-way ordering of messages 有权
标题翻译：用于促进消息的单向排序的装置，系统和方法
公开(公告)号：US08554851B2
公开(公告)日：2013-10-08
申请号：US12889802
申请日：2010-09-24
申请人： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
发明人： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
IPC分类号： G06F15/16
CPC分类号： H04L67/10 , G06F15/17325
摘要： Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.
摘要翻译：用于促进独立消息类别的单向排序的方法，装置和系统。单向消息排序机制有助于在使用消息类的独立路径的互连之间发送的不同消息类别的消息的单向排序。在一个方面，第二消息类的消息可能不会传递第一消息类的消息。此外，当顺序地接收到第一类和第二类的消息时，排序机制确保在转发第二类的消息之前将第一类的消息转发到下一跳并在其中接收。

2. 发明申请

US20120079032A1 APPARATUS, SYSTEM, AND METHODS FOR FACILITATING ONE-WAY ORDERING OF MESSAGES 有权
标题翻译：设备，系统和方法，促进消息的单向订购
公开(公告)号：US20120079032A1
公开(公告)日：2012-03-29
申请号：US12889802
申请日：2010-09-24
申请人： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
发明人： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
IPC分类号： G06F15/16 , G06F5/00 , G06F12/08
CPC分类号： H04L67/10 , G06F15/17325
摘要： Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.
摘要翻译：用于促进独立消息类别的单向排序的方法，装置和系统。单向消息排序机制有助于在使用消息类的独立路径的互连之间发送的不同消息类别的消息的单向排序。在一个方面，第二消息类的消息可能不会传递第一消息类的消息。此外，当顺序地接收到第一类和第二类的消息时，排序机制确保在转发第二类的消息之前将第一类的消息转发到下一跳并在其中接收。

3. 发明申请

US20140214955A1 APPARATUS, SYSTEM, AND METHODS FOR FACILITATINGONE-WAY ORDERING OF MESSAGES 审中-公开
标题翻译：设备，系统和方法，用于方便订购消息
公开(公告)号：US20140214955A1
公开(公告)日：2014-07-31
申请号：US14048254
申请日：2013-10-08
申请人： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
发明人： James R. Vash , Vida Vakilotojar , Bongjin Jung , Yen-Cheng Liu
IPC分类号： H04L29/08
CPC分类号： H04L67/10 , G06F15/17325
摘要： Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.
摘要翻译：用于促进独立消息类别的单向排序的方法，装置和系统。单向消息排序机制有助于在使用消息类的独立路径的互连之间发送的不同消息类别的消息的单向排序。在一个方面，第二消息类的消息可能不会传递第一消息类的消息。此外，当顺序地接收到第一类和第二类的消息时，排序机制确保在转发第二类的消息之前将第一类的消息转发到下一跳并在其中接收。

4. 发明授权

US08020124B2 Various methods and apparatuses for cycle accurate C-models of components 有权
标题翻译：各种方法和装置用于循环精确的C模型的部件
公开(公告)号：US08020124B2
公开(公告)日：2011-09-13
申请号：US12122988
申请日：2008-05-19
申请人： Herve Alexanian , Chien-Chun Chou , Vida Vakilotojar , Grigor Yeghiazaryan
发明人： Herve Alexanian , Chien-Chun Chou , Vida Vakilotojar , Grigor Yeghiazaryan
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G01R31/318314
摘要： Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect. The sub-components of the model at the high level of abstraction are tested in a simulation environment in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction in order to verify the functional accuracy and cycle timing between the two models. After the sub-components are tested, the sub-components of the model at the high level of abstraction may be aggregated into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction.
摘要翻译：描述了用于生成构成互连的硬件组件的模型的各种方法和装置，其有助于在以高抽象级别编码的集成电路中的知识产权块之间的通信，所述集成电路是循环准确地到相应的较低级别构成互连的硬件组件的抽象描述。在高抽象级别的模型的子组件在模拟环境中与在低抽象级别的硬件描述语言中编码的模型的相同子组件并行进行测试，以验证功能精度和两个模型之间的循环时序。在子组件被测试之后，在高抽象级别的模型的子组件可以在抽象的高水平聚合成单个模型，其功能准确并且在低抽象级别对模型进行周期准确。

5. 发明授权

US09495290B2 Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering 有权
标题翻译：各种方法和设备，以支持对多个目标的未完成请求，同时保持事务顺序
公开(公告)号：US09495290B2
公开(公告)日：2016-11-15
申请号：US12144987
申请日：2008-06-24
申请人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
发明人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
IPC分类号： G06F9/46 , G06F9/455 , G06F12/06 , G06F15/173
CPC分类号： G11C7/1072 , G06F12/0607 , G06F15/17375 , Y02D10/13
摘要： A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.
摘要翻译：描述了一种方法，装置和系统，其通常涉及具有实现内部控制的互连的集成电路。集成电路中的互连通信发起者知识产权（IP）核心和耦合到互连的目标IP核之间的交易。互连实现逻辑，其被配置为支持从第一发起方IP核向多个目标IP核发出的多个事务，同时维持事务内的预期执行顺序。在从相同的第一起始IP核发送到第一目标IP核的第一事务完成之前，该逻辑支持将从第一发起者IP核发送到第二目标IP核的第二事务，同时确保第一事务完成之前同时确保在第一事务和第二事务期间的预期执行顺序。该逻辑不包括任何重新排序缓冲。

6. 发明授权

US09292436B2 Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary 有权
标题翻译：用于支持该事务中的数据地址序列跨越交织的信道地址边界的事务的各种方法和装置
公开(公告)号：US09292436B2
公开(公告)日：2016-03-22
申请号：US12145052
申请日：2008-06-24
申请人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
发明人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
IPC分类号： G06F12/06 , G06F15/173
CPC分类号： G11C7/1072 , G06F12/0607 , G06F15/17375 , Y02D10/13
摘要： A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.
摘要翻译：描述了一种方法，装置和系统，其通常涉及到目标IP核的互连路由事务，包括构成第一聚合目标的两个或更多个信道。两个或更多个通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。互连实现斩波逻辑，以将来自第一起始IP的核心的单个事务从第一发起者IP核中切出，该第一发起者IP核的地址序列跨越第一信道的信道地址边界到第一聚合目标内的第二信道，成为两个或多个突发事务。第一切碎突发事务被切碎以适合第一通道的地址边界内，并且第二切断突发事务被切碎以适合于第二通道的地址边界内。

7. 发明申请

US20080320268A1 INTERCONNECT IMPLEMENTING INTERNAL CONTROLS 有权
标题翻译：互连实现内部控制
公开(公告)号：US20080320268A1
公开(公告)日：2008-12-25
申请号：US12144883
申请日：2008-06-24
申请人： Drew E. Wingard , Chien-Chun Chou , Ian Andrew Swarbrick , Stephen W. Hamilton , Vida Vakilotojar
发明人： Drew E. Wingard , Chien-Chun Chou , Ian Andrew Swarbrick , Stephen W. Hamilton , Vida Vakilotojar
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G11C7/1072 , G06F12/0607 , G06F15/17375 , Y02D10/13
摘要： In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.
摘要翻译：在一个实施例中，用于集成电路的互连传送一个或多个启动器知识产权（IP）核与耦合到互连的多个目标IP核之间的事务。两个或多个内存通道组成目标IP内核的第一个聚合目标。两个或多个内存通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。互连实现斩波逻辑以将从第一存储器通道的存储器通道地址边界跨越第一聚合目标内的第二存储器通道的单独的二维（2D）事务转换为具有大于1的高度值的两个或更多个2D事务，以及步长和宽度尺寸，其被切碎以适合于第一聚集目标的存储器通道地址边界。

8. 发明申请

US20080320254A1 VARIOUS METHODS AND APPARATUS TO SUPPORT TRANSACTIONS WHOSE DATA ADDRESS SEQUENCE WITHIN THAT TRANSACTION CROSSES AN INTERLEAVED CHANNEL ADDRESS BOUNDARY 有权
标题翻译：各种方法和设备支持交易之间的数据地址顺序交叉交叉通道地址边界
公开(公告)号：US20080320254A1
公开(公告)日：2008-12-25
申请号：US12145052
申请日：2008-06-24
申请人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
发明人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
IPC分类号： G06F12/06
CPC分类号： G11C7/1072 , G06F12/0607 , G06F15/17375 , Y02D10/13
摘要： A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.
摘要翻译：描述了一种方法，装置和系统，其通常涉及到目标IP核的互连路由事务，包括构成第一聚合目标的两个或更多个信道。两个或更多个通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。互连实现斩波逻辑，以将来自第一起始IP的核心的单个事务从第一发起者IP核中切出，该第一发起者IP核的地址序列跨越第一信道的信道地址边界到第一聚合目标内的第二信道，成为两个或多个突发事务。第一切碎突发事务被切碎以适合第一通道的地址边界内，并且第二切断突发事务被切碎以适合于第二通道的地址边界内。

9. 发明申请

US20090235020A1 VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING 有权
标题翻译：各种方法和地址倾斜装置
公开(公告)号：US20090235020A1
公开(公告)日：2009-09-17
申请号：US12402704
申请日：2009-03-12
申请人： Krishnan Srinivasan , Drew E. Wingard , Vida Vakilotojar , Chien-Chun Chou
发明人： Krishnan Srinivasan , Drew E. Wingard , Vida Vakilotojar , Chien-Chun Chou
IPC分类号： G06F12/06 , G06F13/28
CPC分类号： G06F12/0607
摘要： Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit.
摘要翻译：描述了用于存储器调度器的各种方法和装置。存储器调度器耦合到包括一组存储器的目标存储器核心。存储器调度器包含两个或多个可配置的地址拼接功能，用于将请求中请求的数据的输入地址变换到目标存储器核，以确定存储器组中的哪些物理地址将用于第一请求。两个或多个可配置的地址拼接功能可由用户编程，以在目标存储器核心中创建两个或更多明显不同的存储器区域。每个存储器区域都有自己的不同的平铺功能，基于用户选择的配置参数1）和2）存储在存储器调度器中的平铺寄存器中。多个拼接功能被配置为在集成电路中同时运行。

10. 发明申请

US20080320476A1 VARIOUS METHODS AND APPARATUS TO SUPPORT OUTSTANDING REQUESTS TO MULTIPLE TARGETS WHILE MAINTAINING TRANSACTION ORDERING 有权
标题翻译：支持在维护交易订单时支持多项目标要求的各种方法和设备
公开(公告)号：US20080320476A1
公开(公告)日：2008-12-25
申请号：US12144987
申请日：2008-06-24
申请人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
发明人： Drew E. Wingard , Chien-Chun Chou , Stephen W. Hamilton , Ian Andrew Swarbrick , Vida Vakilotojar
IPC分类号： G06F9/46
CPC分类号： G11C7/1072 , G06F12/0607 , G06F15/17375 , Y02D10/13
摘要： A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.
摘要翻译：描述了一种方法，装置和系统，其通常涉及具有实现内部控制的互连的集成电路。集成电路中的互连通信发起者知识产权（IP）核心和耦合到互连的目标IP核之间的交易。互连实现逻辑，其被配置为支持从第一发起方IP核向多个目标IP核发出的多个事务，同时维持事务内的预期执行顺序。在从相同的第一起始IP核发送到第一目标IP核的第一事务完成之前，该逻辑支持将从第一发起者IP核发送到第二目标IP核的第二事务，同时确保第一事务完成之前同时确保在第一事务和第二事务期间的预期执行顺序。该逻辑不包括任何重新排序缓冲。

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