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1. 发明申请

US20090235020A1 VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING 有权
标题翻译：各种方法和地址倾斜装置
公开(公告)号：US20090235020A1
公开(公告)日：2009-09-17
申请号：US12402704
申请日：2009-03-12
申请人： Krishnan Srinivasan , Drew E. Wingard , Vida Vakilotojar , Chien-Chun Chou
发明人： Krishnan Srinivasan , Drew E. Wingard , Vida Vakilotojar , Chien-Chun Chou
IPC分类号： G06F12/06 , G06F13/28
CPC分类号： G06F12/0607
摘要： Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit.
摘要翻译：描述了用于存储器调度器的各种方法和装置。存储器调度器耦合到包括一组存储器的目标存储器核心。存储器调度器包含两个或多个可配置的地址拼接功能，用于将请求中请求的数据的输入地址变换到目标存储器核，以确定存储器组中的哪些物理地址将用于第一请求。两个或多个可配置的地址拼接功能可由用户编程，以在目标存储器核心中创建两个或更多明显不同的存储器区域。每个存储器区域都有自己的不同的平铺功能，基于用户选择的配置参数1）和2）存储在存储器调度器中的平铺寄存器中。多个拼接功能被配置为在集成电路中同时运行。

2. 发明授权

US08108648B2 Various methods and apparatus for address tiling 有权
标题翻译：各种地址拼贴方法和装置
公开(公告)号：US08108648B2
公开(公告)日：2012-01-31
申请号：US12402704
申请日：2009-03-12
申请人： Krishnan Srinivasan , Drew E. Wingard , Vida Vakilotojar , Chien-Chun Chou
发明人： Krishnan Srinivasan , Drew E. Wingard , Vida Vakilotojar , Chien-Chun Chou
IPC分类号： G06F12/00
CPC分类号： G06F12/0607
摘要： Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit.
摘要翻译：描述了用于存储器调度器的各种方法和装置。存储器调度器耦合到包括一组存储器的目标存储器核心。存储器调度器包含两个或多个可配置的地址拼接功能，用于将请求中请求的数据的输入地址变换到目标存储器核，以确定存储器组中的哪些物理地址将用于第一请求。两个或多个可配置的地址拼接功能可由用户编程，以在目标存储器核心中创建两个或更多明显不同的存储器区域。每个存储器区域都有自己的不同的平铺功能，基于用户选择的配置参数1）和2）存储在存储器调度器中的平铺寄存器中。多个拼接功能被配置为在集成电路中同时运行。

3. 发明授权

US08972995B2 Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads 有权
标题翻译：同时执行每个线程以及线程内和跨两个或多个线程的每个标签内存访问调度的设备和方法
公开(公告)号：US08972995B2
公开(公告)日：2015-03-03
申请号：US12852355
申请日：2010-08-06
申请人： Krishnan Srinivasan , Ruben Khazhakyan , Harutyan Aslanyan , Drew E. Wingard , Chien-Chun Chou
发明人： Krishnan Srinivasan , Ruben Khazhakyan , Harutyan Aslanyan , Drew E. Wingard , Chien-Chun Chou
IPC分类号： G06F9/46 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34 , G06F15/00 , G06F15/76 , G06F9/52
CPC分类号： G06F9/526 , G06F12/0879 , G06F12/0882
摘要： A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.
摘要翻译：集成电路包括启动器知识产权（IP）核心，目标IP核，互连以及标签和线程逻辑的方法，装置和系统。目标IP核可以包括耦合到发起者IP核的存储器。另外，互连可以允许集成电路在一个或多个启动器知识产权（IP）核心和耦合到互连的一个或多个目标IP核之间传送事务。标签和线程逻辑可以被配置为同时执行线程内和跨多个线程的每线程和每标签内存访问调度，使得标签和线程逻辑管理标签和线程以允许每标签和每个线程调度的内存从发起者IP内核访问来自发起者IP核的请求的初始发布顺序的顺序的请求。

4. 发明申请

US20100042759A1 VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING AND CHANNEL INTERLEAVING THROUGHOUT THE INTEGRATED SYSTEM 有权
标题翻译：各种方法和设备通过集成系统进行地址倾斜和通道交互
公开(公告)号：US20100042759A1
公开(公告)日：2010-02-18
申请号：US12573669
申请日：2009-10-05
申请人： Krishnan Srinivasan , Drew E. Wingard , Chien-Chun Chou
发明人： Krishnan Srinivasan , Drew E. Wingard , Chien-Chun Chou
IPC分类号： G06F13/32
CPC分类号： G06F12/0607 , G06F13/4295
摘要： Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.
摘要翻译：针对具有多个通道的目标描述了各种方法和装置。地址解码逻辑被配置为实现从单个突发请求到构成聚合目标的两个或多个存储器通道的分配。地址解码逻辑实现信道选择散列函数，以允许来自每个单独突发请求的请求以构成聚合目标的信道循环顺序的非线性顺序模式分布在两个或更多个信道中。

5. 发明授权

US08438320B2 Various methods and apparatus for address tiling and channel interleaving throughout the integrated system 有权
标题翻译：用于整个集成系统中的地址拼接和信道交织的各种方法和装置
公开(公告)号：US08438320B2
公开(公告)日：2013-05-07
申请号：US12573669
申请日：2009-10-05
申请人： Krishnan Srinivasan , Drew E. Wingard , Chien-Chun Chou
发明人： Krishnan Srinivasan , Drew E. Wingard , Chien-Chun Chou
IPC分类号： G06F13/00
CPC分类号： G06F12/0607 , G06F13/4295
摘要： Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.
摘要翻译：针对具有多个通道的目标描述了各种方法和装置。地址解码逻辑被配置为实现从单个突发请求到构成聚合目标的两个或多个存储器通道的分配。地址解码逻辑实现信道选择散列函数，以允许来自每个单独突发请求的请求以构成聚合目标的信道循环顺序的非线性顺序模式分布在两个或更多个信道中。

6. 发明授权

US08190804B1 Various methods and apparatus for a memory scheduler with an arbiter 有权
标题翻译：用于具有仲裁器的存储器调度器的各种方法和装置
公开(公告)号：US08190804B1
公开(公告)日：2012-05-29
申请号：US12402707
申请日：2009-03-12
申请人： Krishnan Srinivasan , Drew E. Wingard
发明人： Krishnan Srinivasan , Drew E. Wingard
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1615
摘要： Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.
摘要翻译：描述了用于存储器调度器的各种方法和装置。存储器调度器具有流水线仲裁器，以确定哪个请求将访问目标存储器核心。流水线在多于一个时钟周期的时间内在仲裁器内分阶段发生。流水线仲裁器使用两个或更多个加权因素影响并行处理的仲裁决策。存储器调度器中的预测调度器使用来自前一周期的数据在当前时钟周期内作出关于请求的仲裁决定，其中作出仲裁决定以提高在集成电路中服务的请求的整体系统效率。

7. 发明授权

US08484397B1 Various methods and apparatus for a memory scheduler with an arbiter 有权
标题翻译：用于具有仲裁器的存储器调度器的各种方法和装置
公开(公告)号：US08484397B1
公开(公告)日：2013-07-09
申请号：US13479578
申请日：2012-05-24
申请人： Krishnan Srinivasan , Drew E. Wingard
发明人： Krishnan Srinivasan , Drew E. Wingard
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1615
摘要： Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.
摘要翻译：描述了用于存储器调度器的各种方法和装置。存储器调度器具有流水线仲裁器，以确定哪个请求将访问目标存储器核心。流水线在多于一个时钟周期的时间内在仲裁器内分阶段发生。流水线仲裁器使用两个或更多个加权因素影响并行处理的仲裁决策。存储器调度器中的预测调度器使用来自前一周期的数据在当前时钟周期内作出关于请求的仲裁决定，其中作出仲裁决定以提高在集成电路中服务的请求的整体系统效率。

8. 发明申请

US20090254525A1 METHOD AND SYSTEM FOR A DATABASE TO MONITOR AND ANALYZE PERFORMANCE OF AN ELECTRONIC DESIGN 有权
标题翻译：用于监视和分析电子设计性能的数据库的方法和系统
公开(公告)号：US20090254525A1
公开(公告)日：2009-10-08
申请号：US12098614
申请日：2008-04-07
申请人： Krishnan Srinivasan , Chien-Chun Chou , Pascal Chauvet
发明人： Krishnan Srinivasan , Chien-Chun Chou , Pascal Chauvet
IPC分类号： G06F7/06 , G06F17/30
CPC分类号： G06F17/3056 , G06F17/30386
摘要： Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design having one or more bus interconnects. A relational database may have defined tables designed for interconnect analysis of transactions occurring between initiator intellectual property (IP) cores and target IP cores of the electronic design. A query tool may be configured to format input data to be stored in the defined tables, and have application programming interfaces to retrieve data from the defined tables based on performing a query. The query tool executes an algorithm based on the query to provide the interconnect analysis.
摘要翻译：描述了提供具有一个或多个总线互连的电子设计的仪器和分析的各种方法和装置。关系数据库可以具有设计用于在电子设计的发起者知识产权（IP）核心和目标IP核之间发生的事务的互连分析的定义表。可以将查询工具配置为格式化要存储在定义的表中的输入数据，并具有应用程序编程接口，以便基于执行查询从定义的表中检索数据。查询工具执行基于查询的算法来提供互连分析。

9. 发明授权

US08229723B2 Performance software instrumentation and analysis for electronic design automation 有权
标题翻译：电子设计自动化的性能软件仪器和分析
公开(公告)号：US08229723B2
公开(公告)日：2012-07-24
申请号：US11952416
申请日：2007-12-07
申请人： Krishnan Srinivasan , Chien-Chun Chou , Drew Wingard
发明人： Krishnan Srinivasan , Chien-Chun Chou , Drew Wingard
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G01R31/31705 , G01R31/318357 , G06F11/3409 , G06F11/3457 , G06F17/5022 , G06F2201/815 , G06F2201/87 , G06F2201/88
摘要： Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design. A method for providing performance instrumentation and analysis of the electronic design includes defining a first and second set of intended software instrumentation test points and an associated first and second set of performance analysis units. The method further includes instrumenting the first and second sets of software instrumentation test points and the associated first and second sets of performance analysis units to a first model and a second model, respectively. The method further includes creating a first and a second set of software instances associated with the first and second sets of intended software instrumentation test points and associated sets of performance analysis units during run time of a first simulation and a second simulation of the electronic design associated with the first model and second model, respectively.
摘要翻译：描述了提供电子设计的仪器和分析的各种方法和装置。提供电子设计的性能测试和分析的方法包括定义第一组和第二组预期的软件测试点以及相关联的第一和第二组性能分析单元。该方法还包括分别将第一和第二组软件仪表测试点和相关联的第一和第二组性能分析单元测试到第一模型和第二模型。该方法还包括在第一次模拟的运行时间和相关联的电子设计的第二仿真期间创建与第一组和第二组预期软件测试点和相关联的性能分析单元组相关联的第一组和第二组软件实例分别是第一个模型和第二个模型。

10. 发明授权

US08073820B2 Method and system for a database to monitor and analyze performance of an electronic design 有权
标题翻译：用于监测和分析电子设计性能的数据库的方法和系统
公开(公告)号：US08073820B2
公开(公告)日：2011-12-06
申请号：US12098614
申请日：2008-04-07
申请人： Krishnan Srinivasan , Chien-Chun Chou , Pascal Chauvet
发明人： Krishnan Srinivasan , Chien-Chun Chou , Pascal Chauvet
IPC分类号： G06F7/00 , G06F17/00 , G06F17/50
CPC分类号： G06F17/3056 , G06F17/30386
摘要： Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design having one or more bus interconnects. A relational database may have defined tables designed for interconnect analysis of transactions occurring between initiator intellectual property (IP) cores and target IP cores of the electronic design. A query tool may be configured to format input data to be stored in the defined tables, and have application programming interfaces to retrieve data from the defined tables based on performing a query. The query tool executes an algorithm based on the query to provide the interconnect analysis.
摘要翻译：描述了提供具有一个或多个总线互连的电子设计的仪器和分析的各种方法和装置。关系数据库可以具有设计用于在电子设计的发起者知识产权（IP）核心和目标IP核之间发生的事务的互连分析的定义表。可以将查询工具配置为格式化要存储在定义的表中的输入数据，并具有应用程序编程接口，以便基于执行查询从定义的表中检索数据。查询工具执行基于查询的算法来提供互连分析。

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