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1. 发明申请

US20080177981A1 APPARATUS AND METHOD FOR DECREASING THE LATENCY BETWEEN INSTRUCTION CACHE AND A PIPELINE PROCESSOR 失效
标题翻译：指令缓存和管道处理器之间延迟延迟的装置和方法
公开(公告)号：US20080177981A1
公开(公告)日：2008-07-24
申请号：US11868557
申请日：2007-10-08
申请人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
发明人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.
摘要翻译：一种用于在流水线处理器中执行指令的方法和装置。由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。

2. 发明授权

US07711930B2 Apparatus and method for decreasing the latency between instruction cache and a pipeline processor 失效
标题翻译：用于减少指令高速缓存和流水线处理器之间的等待时间的装置和方法
公开(公告)号：US07711930B2
公开(公告)日：2010-05-04
申请号：US11868557
申请日：2007-10-08
申请人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
发明人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.
摘要翻译：一种用于在流水线处理器中执行指令的方法和装置。由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。

3. 发明授权

US07281120B2 Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor 失效
标题翻译：用于减少指令高速缓存和流水线处理器之间的等待时间的装置和方法
公开(公告)号：US07281120B2
公开(公告)日：2007-10-09
申请号：US10810235
申请日：2004-03-26
申请人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
发明人： James N. Dieffenderfer , Richard W. Doing , Brian M. Stempel , Steven R. Testa , Kenichi Tsuchiya
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3867
摘要： A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.
摘要翻译：一种用于在流水线处理器中执行指令的方法和装置。由于执行分支校正，或当中断改变指令流的序列时，该方法减少了在处理流中发生气泡时指令高速缓存和流水线处理器之间的等待时间。当用于检测分支预测的解码级和相关指令队列位置具有表示处理流中的气泡的无效数据时，等待时间减少。执行指令并行插入到解码级和指令队列中，从而将流水线级的长度减少一个周期。

4. 发明授权

US07321954B2 Method for software controllable dynamically lockable cache line replacement system 有权
标题翻译：软件可控动态锁定缓存线替换系统的方法
公开(公告)号：US07321954B2
公开(公告)日：2008-01-22
申请号：US10915982
申请日：2004-08-11
申请人： James N. Dieffenderfer , Richard W. Doing , Brian E. Frankel , Kenichi Tsuchiya
发明人： James N. Dieffenderfer , Richard W. Doing , Brian E. Frankel , Kenichi Tsuchiya
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F12/126 , G06F12/125
摘要： An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.
摘要翻译：用于跟踪关联高速缓存行的访问的LRU数组和方法。缓存中最近访问的行在表中标识，并且可以阻止缓存行被替换。 LRU阵列包含具有代表相关高速缓存的每行的数据行的数据阵列，其具有公共地址部分。高速缓存行的第一组数据相对于每隔一个方式识别每个方式的高速缓存行的相对年龄。第二组数据识别一条路线是否不被替换。对于高速缓存行替换，高速缓存控制器将使用LRU阵列的内容来选择最近访问的行，考虑第一组数据的值，以及第二组数据的值，指示一种方式是否为锁定对LRU的更新发生在每个预取或提取行之后，或者替换高速缓存中的另一行时。

5. 发明授权

US08131976B2 Tracking effective addresses in an out-of-order processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US08131976B2
公开(公告)日：2012-03-06
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/26 , G06F9/34
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

6. 发明申请

US20090063819A1 Method and Apparatus for Dynamically Managing Instruction Buffer Depths for Non-Predicted Branches 失效
标题翻译：用于动态管理非预测分支的指令缓冲区深度的方法和装置
公开(公告)号：US20090063819A1
公开(公告)日：2009-03-05
申请号：US11845838
申请日：2007-08-28
申请人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
发明人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3804
摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
摘要翻译：用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径。

7. 发明申请

US20080086596A1 Apparatus and Method for Supporting Simultaneous Storage of Trace and Standard Cache Lines 有权
标题翻译：支持跟踪和标准缓存线同时存储的装置和方法
公开(公告)号：US20080086596A1
公开(公告)日：2008-04-10
申请号：US11538445
申请日：2006-10-04
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M. V. V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M. V. V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/0875 , G06F12/0897 , G06F2212/6082
摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。描述了一种用于索引到高速缓存并选择所需行的机制。对缓存中包含哪些行进行控制。当在标签比较步骤中匹配时，提供在轨迹线和常规线之间的选择。

8. 发明申请

US20080086595A1 Apparatus and Method for Saving Power in a Trace Cache 失效
标题翻译：用于在跟踪缓存中节省功率的装置和方法
公开(公告)号：US20080086595A1
公开(公告)日：2008-04-10
申请号：US11538458
申请日：2006-10-04
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M. V. V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M. V. V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F9/3808 , G06F2212/1028 , Y02D10/13
摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。通过引导访问存储在缓存中的行并相对于中央处理器时钟速度降低缓存时钟速度来节省功率。

9. 发明申请

US20110131394A1 APPARATUS AND METHOD FOR USING BRANCH PREDICTION HEURISTICS FOR DETERMINATION OF TRACE FORMATION READINESS 失效
标题翻译：使用分支预测机制确定跟踪形成准备的装置和方法
公开(公告)号：US20110131394A1
公开(公告)日：2011-06-02
申请号：US13016144
申请日：2011-01-28
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/40 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。缓存中的跟踪行的形成在系统的初始操作中被延迟，以确保存储的跟踪线的质量。

10. 发明申请

US20100262806A1 Tracking Effective Addresses in an Out-of-Order Processor 有权
标题翻译：跟踪无序处理器中的有效地址
公开(公告)号：US20100262806A1
公开(公告)日：2010-10-14
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译：在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。

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