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1. 发明申请

US20070130438A1 Atomic operation involving processors with different memory transfer operation sizes 有权
标题翻译：具有不同内存传输操作大小的处理器的原子操作
公开(公告)号：US20070130438A1
公开(公告)日：2007-06-07
申请号：US11291306
申请日：2005-12-01
申请人： James Marr , John Bates , Attila Vass , Tatsuya Iwamoto
发明人： James Marr , John Bates , Attila Vass , Tatsuya Iwamoto
IPC分类号： G06F13/28
CPC分类号： G06F9/3879 , G06F9/526 , G06F2209/521
摘要： Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines. A main memory address containing a primitive is divided into a parity byte and two or more portions, wherein the parity byte includes at least one bit. A value of the parity byte determines which of the two or more portions is a valid portion and which of them is an invalid portion. The primitive is of a memory size that is larger than a maximum size for atomic operation with the PPE and less than or equal to a maximum size for atomic operation with the SPE. Read with reservation and conditional write instructions are used by both the PPE and SPE to access or update a value of the atomic.
摘要翻译：原子操作可以在具有主存储器和两个或更多个处理器的处理器系统上实现，所述处理器包括在不同大小的寄存器线上操作的功率处理器元件（PPE）和协同处理器元件（SPE）。包含原语的主存储器地址被划分为奇偶校验字节和两个或多个部分，其中奇偶校验字节包括至少一个位。奇偶校验字节的值确定两个或多个部分中的哪一个是有效部分，哪些是无效部分。原始内存大小大于使用PPE进行原子操作的最大大小，小于或等于使用SPE进行原子操作的最大大小。读取预留和条件写入指令由PPE和SPE使用来访问或更新原子的值。

2. 发明授权

US07398368B2 Atomic operation involving processors with different memory transfer operation sizes 有权
标题翻译：具有不同内存传输操作大小的处理器的原子操作
公开(公告)号：US07398368B2
公开(公告)日：2008-07-08
申请号：US11291306
申请日：2005-12-01
申请人： James E. Marr , John P. Bates , Attila Vass , Tatsuya Iwamoto
发明人： James E. Marr , John P. Bates , Attila Vass , Tatsuya Iwamoto
IPC分类号： G06F12/00
CPC分类号： G06F9/3879 , G06F9/526 , G06F2209/521
摘要： Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines. A main memory address containing a primitive is divided into a parity byte and two or more portions, wherein the parity byte includes at least one bit. A value of the parity byte determines which of the two or more portions is a valid portion and which of them is an invalid portion. The primitive is of a memory size that is larger than a maximum size for atomic operation with the PPE and less than or equal to a maximum size for atomic operation with the SPE. Read with reservation and conditional write instructions are used by both the PPE and SPE to access or update a value of the atomic.
摘要翻译：原子操作可以在具有主存储器和两个或更多个处理器的处理器系统上实现，所述处理器包括在不同大小的寄存器线上操作的功率处理器元件（PPE）和协同处理器元件（SPE）。包含原语的主存储器地址被划分为奇偶校验字节和两个或多个部分，其中奇偶校验字节包括至少一个位。奇偶校验字节的值确定两个或多个部分中的哪一个是有效部分，哪些是无效部分。原始内存大小大于使用PPE进行原子操作的最大大小，小于或等于使用SPE进行原子操作的最大大小。读取预留和条件写入指令由PPE和SPE使用来访问或更新原子的值。

3. 发明申请

US20130273378A1 INTERLAYER FOR LAMINATED GLASS AND LAMINATED GLASS 审中-公开
标题翻译：层压玻璃和层压玻璃的层间隔
公开(公告)号：US20130273378A1
公开(公告)日：2013-10-17
申请号：US13976547
申请日：2011-12-28
申请人： Tatsuya Iwamoto , Ryousuke Komatsu , Kohei Kani , Shogo Yoshida
发明人： Tatsuya Iwamoto , Ryousuke Komatsu , Kohei Kani , Shogo Yoshida
IPC分类号： B32B17/10
CPC分类号： B32B17/10761 , B32B17/10036 , B32B2250/03 , B32B2307/102 , B32B2307/51 , B32B2419/00 , B32B2605/00 , Y10T428/31627 , Y10T428/31859
摘要： The present invention provides an interlayer film for a laminated glass which can suppress bubble formation and bubble growth in the laminated glass. An interlayer film for a laminated glass according to the present invention includes a first layer and a second layer laminated on one face of the first layer, each of the first layer and the second layer contains a polyvinyl acetal resin, contains a carboxylic acid-modified polyvinyl acetal resin, or contains both a polyvinyl acetal resin and a carboxylic acid-modified polyvinyl acetal resin, each of the first layer and the second layer contains a plasticizer, and when the first layer does not contain the carboxylic acid-modified polyvinyl acetal resin, the first layer contains a compound having a boron atom.
摘要翻译：本发明提供一种能够抑制夹层玻璃中的气泡形成和气泡生长的夹层玻璃用中间膜。根据本发明的夹层玻璃用中间膜包括层压在第一层的一个面上的第一层和第二层，第一层和第二层中的每一层包含聚乙烯醇缩醛树脂，其包含羧酸改性的聚乙烯醇缩醛树脂，或含有聚乙烯醇缩醛树脂和羧酸改性聚乙烯醇缩醛树脂，第一层和第二层均含有增塑剂，当第一层不含有羧酸改性的聚乙烯醇缩醛树脂，第一层含有具有硼原子的化合物。

4. 发明申请

US20130183532A1 LAMINATED GLASS INTERLAYER AND LAMINATED GLASS 有权
标题翻译：层压玻璃中间层和层压玻璃
公开(公告)号：US20130183532A1
公开(公告)日：2013-07-18
申请号：US13876145
申请日：2011-09-30
申请人： Michio Shimamoto , Shota Matsuda , Sinyul Yang , Kohei Kani , Tatsuya Iwamoto
发明人： Michio Shimamoto , Shota Matsuda , Sinyul Yang , Kohei Kani , Tatsuya Iwamoto
IPC分类号： B32B17/10
CPC分类号： B32B17/10605 , B32B17/10036 , B32B17/10761 , B32B2250/03 , B32B2307/102 , B60J3/007 , C08K5/0016 , C08K2201/014 , Y10T428/31627 , Y10T428/3163 , Y10T428/31649 , Y10T428/31859 , Y10T428/31928 , Y10T428/31942 , Y10T428/31946 , C08L29/14
摘要： The present invention aims to provide an intermediate film for laminated glass which, in the case of being used for constituting a laminated glass, enables to improve the sound-insulating property of the obtained laminated glass, and a laminated glass. The intermediate film 1 for laminated glass of the present invention comprises a first layer 2 which contains a polyvinyl acetal resin and a plasticizer, and the polyvinyl acetal resin and the first plasticizer are a polyvinyl acetal resin and a first plasticizer which have a cloud point of 5° C. or lower when the cloud point is measured using a solution prepared by dissolving 8 parts by weight of the polyvinyl acetal resin in 100 parts by weight of the first plasticizer; and the laminated glass 11 of the present invention comprises first and second components for laminated glass, and the intermediate film 1 for laminated glass sandwiched between the first and second components for laminated glass.
摘要翻译：本发明的目的在于提供一种用于夹层玻璃的中间膜，在用于构成夹层玻璃的情况下，能够提高所获得的夹层玻璃和夹层玻璃的隔音性。本发明的夹层玻璃用中间膜1包括含有聚乙烯醇缩醛树脂和增塑剂的第一层2，聚乙烯醇缩醛树脂和第一增塑剂是聚乙烯醇缩醛树脂和第一增塑剂，其浊点为当使用通过将8重量份的聚乙烯醇缩醛树脂溶解在100重量份的第一增塑剂中制备的溶液来测量浊点时，为5℃或更低; 并且本发明的夹层玻璃11包括夹层玻璃的第一和第二部件和夹在夹层玻璃的第一和第二部件之间的夹层玻璃用中间膜1。

5. 发明授权

US08316220B2 Operating processors over a network 有权
标题翻译：通过网络操作处理器
公开(公告)号：US08316220B2
公开(公告)日：2012-11-20
申请号：US11238086
申请日：2005-09-27
申请人： Tatsuya Iwamoto
发明人： Tatsuya Iwamoto
IPC分类号： G06F15/16
CPC分类号： G06F9/3865 , G06F9/4856
摘要： Processors, data structures and methods for operating two or more processors over a network are disclosed. A processor can load, store and save information relating to the operation of one or more of its secondary processors in a unit of migration that includes either contents of exclusively associated memories of two or more secondary processors related to the execution state of a suspended process or contents of exclusively associated memories of one or more secondary processors related to the execution state of a suspended process and shared initialized data for the process. Such a unit of migration may be embodied in a processor readable medium.
摘要翻译：公开了用于在网络上操作两个或多个处理器的处理器，数据结构和方法。处理器可以以包括与暂停进程的执行状态相关的两个或更多个二级处理器的专有关联存储器的内容的迁移单元来加载，存储和保存与其一个或多个二级处理器的操作有关的信息，或者与暂停进程的执行状态相关的一个或多个次要处理器的专用关联存储器的内容和用于该处理的共享初始化数据。这样的迁移单元可以体现在处理器可读介质中。

6. 发明申请

US20120244329A1 INTERLAYER FOR LAMINATED GLASS, AND LAMINATED GLASS 有权
标题翻译：层压玻璃和层压玻璃的层间隔层
公开(公告)号：US20120244329A1
公开(公告)日：2012-09-27
申请号：US13514013
申请日：2010-12-28
申请人： Tatsuya Iwamoto , Kohei Kani
发明人： Tatsuya Iwamoto , Kohei Kani
IPC分类号： B32B27/30 , B32B17/10 , B32B27/08 , B32B7/02
CPC分类号： B32B17/10761 , B32B17/10605 , B32B27/08 , B32B27/306 , C08K5/0016 , C08K5/103 , Y10T428/2495 , Y10T428/31627 , Y10T428/3163 , Y10T428/31859 , Y10T428/31909 , Y10T428/31942 , Y10T428/31946 , C08L29/14
摘要： The present invention provides an interlayer film for a laminated glass which can suppress bubble formation and bubble growth in the laminated glass. An interlayer film 1 for a laminated glass includes a first layer 2 and a second layer 3 laminated on one face 2a of the first layer 2. Each of the first layer 2 and the second layer 3 contains a polyvinyl acetal resin and a plasticizer. The polyvinyl acetal resin in the first layer 2 is obtained by acetalizing a polyvinyl alcohol resin that has a degree of polymerization exceeding 3000.
摘要翻译：本发明提供一种能够抑制夹层玻璃中的气泡形成和气泡生长的夹层玻璃用中间膜。夹层玻璃用中间膜1包括层叠在第一层2的一个面2a上的第一层2和第二层3.第一层2和第二层3中的每一层含有聚乙烯醇缩醛树脂和增塑剂。第一层2中的聚乙烯醇缩醛树脂通过缩聚聚合度超过3000的聚乙烯醇树脂而获得。

7. 发明授权

US07386642B2 IO direct memory access system and method 有权
标题翻译： IO直接内存访问系统和方法
公开(公告)号：US07386642B2
公开(公告)日：2008-06-10
申请号：US11045767
申请日：2005-01-28
申请人： Keisuke Inoue , Tatsuya Iwamoto
发明人： Keisuke Inoue , Tatsuya Iwamoto
IPC分类号： G06F11/00
CPC分类号： G06F13/28
摘要： Direct memory access is provided for each member of a group of IO devices organized into groups. Direct memory access for each IO device is performed in a predetermined order based on the predetermined groups, and may be completed by notification by an interrupt request. A predetermined time delay may be specified between each memory access by each IO device of a predetermined group.
摘要翻译：为组织的组的一组IO设备的每个成员提供直接存储器访问。基于预定组，以预定的顺序执行每个IO设备的直接存储器访问，并且可以通过中断请求的通知来完成。可以在预定组的每个IO设备的每个存储器访问之间指定预定的时间延迟。

8. 发明申请

US20060195824A1 Methods and apparatus for segmented stack management in a processor system 有权
标题翻译：处理器系统中分段堆栈管理的方法和装置
公开(公告)号：US20060195824A1
公开(公告)日：2006-08-31
申请号：US11068242
申请日：2005-02-28
申请人： Tatsuya Iwamoto
发明人： Tatsuya Iwamoto
IPC分类号： G06F9/44
CPC分类号： G06F9/4484 , G06F12/0811
摘要： Methods and apparatus provide for allocating a first stack module in response to a first function call of a software program running on a processing system; and allocating a second stack module in response to a second function call of the software program, wherein the second stack module is non-contiguous with respect to the first stack module.
摘要翻译：方法和装置提供响应于在处理系统上运行的软件程序的第一功能调用来分配第一堆栈模块; 以及响应于所述软件程序的第二函数调用而分配第二堆栈模块，其中所述第二堆栈模块相对于所述第一堆栈模块是不连续的。

9. 发明申请

US20060075394A1 Dynamic loading and unloading for processing unit 审中-公开
标题翻译：动态加载和卸载处理单元
公开(公告)号：US20060075394A1
公开(公告)日：2006-04-06
申请号：US10957158
申请日：2004-10-01
申请人： Tatsuya Iwamoto
发明人： Tatsuya Iwamoto
IPC分类号： G06F9/44
CPC分类号： G06F9/44521 , G06F12/08 , G06F2212/251 , G06F2212/253
摘要： Methods and apparatus are provided for enhanced instruction handling in processing environments. A program reference may be associated with one or more program modules. The program modules may be loaded into local memory and information, such as code or data, may be obtained from the program modules based on the program reference. New program modules can be formed based on existing program modules. Generating direct references within a program module and avoiding indirect references between program modules can optimize the new program modules. A program module may be preloaded in the local memory based upon an insertion point. The insertion point can be determined statistically. The invention is particularly beneficial for multiprocessor systems having limited amounts of memory.
摘要翻译：为处理环境中的指令处理提供了方法和装置。程序引用可以与一个或多个程序模块相关联。可以将程序模块加载到本地存储器中，并且可以基于程序引用从程序模块获得诸如代码或数据的信息。可以基于现有的程序模块形成新的程序模块。在程序模块中生成直接引用并避免程序模块间的间接引用可以优化新的程序模块。可以基于插入点将程序模块预加载到本地存储器中。可以统计确定插入点。本发明对于具有有限量的存储器的多处理器系统是特别有益的。

10. 发明申请

US20050188373A1 Methods and apparatus for task management in a multi-processor system 失效
标题翻译：多处理器系统中任务管理的方法和装置
公开(公告)号：US20050188373A1
公开(公告)日：2005-08-25
申请号：US10783246
申请日：2004-02-20
申请人： Keisuke Inoue , Tatsuya Iwamoto , Masahiro Yasue
发明人： Keisuke Inoue , Tatsuya Iwamoto , Masahiro Yasue
IPC分类号： G06F9/50 , G06F9/445 , G06F9/46 , G06F9/48
CPC分类号： G06F9/4881 , G06F9/4411 , G06F9/5038 , G06F2209/483 , G06F2209/484
摘要： Methods and apparatus are provided for managing processor tasks in a multi-processor computing system. The system is operable to store the processor tasks in a shared memory that may be accessed by a plurality of sub-processing units of the multi-processor computing system; and permit the sub-processing units to determine which of the processor tasks should be copied from the shared memory and executed based on priorities of the processor tasks.
摘要翻译：提供了用于在多处理器计算系统中管理处理器任务的方法和装置。该系统可操作以将处理器任务存储在可由多处理器计算系统的多个子处理单元访问的共享存储器中; 并且允许子处理单元基于处理器任务的优先级来确定应该从共享存储器复制哪个处理器任务并执行。

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