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1. 发明授权

US08874885B2 Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs 有权
标题翻译：通过故意停止分支指令，直到接收到延迟的分支预测或发生超时来减轻前瞻分支预测等待时间
公开(公告)号：US08874885B2
公开(公告)日：2014-10-28
申请号：US12029543
申请日：2008-02-12
申请人： James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
发明人： James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/3806 , G06F9/3836 , G06F9/3848
摘要： Embodiments relate to mitigation of lookahead branch predication latency. An aspect includes receiving an instruction address in an instruction cache for fetching instructions in a microprocessor pipeline. Another aspect includes receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline. Another aspect includes determining, by the branch presence predictor, presence of a branch instruction in the instructions being fetched, wherein the branch instruction is predictable by the branch target buffer, and any indication of the instruction address not written to the branch target buffer is also not written to the branch presence predictor. Another aspect includes, based on receipt of an indication that the branch instruction is present from the branch presence predictor, holding the branch instruction. Another aspect includes, based on receipt of a branch prediction corresponding to the branch instruction from the branch target buffer, releasing said held branch instruction to the pipeline.
摘要翻译：实施例涉及减轻前瞻分支预测延迟。一个方面包括在指令高速缓存中接收用于在微处理器流水线中取指令的指令地址。另一方面包括在耦合到微处理器流水线的分支存在预测器中接收指令地址。另一方面包括通过分支存在预测器确定在所取出的指令中存在分支指令，其中分支指令可由分支目标缓冲器预测，并且未写入分支目标缓冲器的指令地址的任何指示也是没有写入分支存在预测器。另一方面包括：基于从分支存在预测器接收到分支指令的指示，保持分支指令。另一方面包括基于从分支目标缓冲器接收到与分支指令相对应的分支预测，将所述保持的分支指令释放到流水线。

2. 发明申请

US20130339683A1 INSTRUCTION FILTERING 有权
标题翻译：指令过滤
公开(公告)号：US20130339683A1
公开(公告)日：2013-12-19
申请号：US13523170
申请日：2012-06-14
申请人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
发明人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/30 , G06F9/30047 , G06F9/3005 , G06F9/3806 , G06F9/3836
摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.
摘要翻译：实施例涉及指令过滤。一个方面包括用于指令过滤的系统。该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。基于标记的指令文本来防止跟踪指令逻辑块的动作。

3. 发明授权

US07913068B2 System and method for providing asynchronous dynamic millicode entry prediction 失效
标题翻译：提供异步动态millicode条目预测的系统和方法
公开(公告)号：US07913068B2
公开(公告)日：2011-03-22
申请号：US12035109
申请日：2008-02-21
申请人： James J. Bonanno , Brian R. Prasky , John G. Rell, Jr. , Anthony Saporito , Chung-Lung Kevin Shum
发明人： James J. Bonanno , Brian R. Prasky , John G. Rell, Jr. , Anthony Saporito , Chung-Lung Kevin Shum
IPC分类号： G06F9/42
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/30174 , G06F9/3806
摘要： A system and method for asynchronous dynamic millicode entry prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information. The branch information includes: a branch type indicating that the branch represents a millicode entry (mcentry) instruction targeting a millicode subroutine, and an instruction length code (ILC) associated with the mcentry instruction. The system also includes search logic to perform a method. The method includes locating a branch address in the BTB for the mcentry instruction targeting the millicode subroutine, and determining a return address to return from the millicode subroutine as a function of the an instruction address of the mcentry instruction and the ILC. The system further includes instruction fetch controls to fetch instructions of the millicode subroutine asynchronous to the search logic. The search logic may also operate asynchronous with respect to an instruction decode unit.
摘要翻译：提供了一种用于在处理器中进行异步动态毫代码入口预测的系统和方法。该系统包括用于保存分支信息的分支目标缓冲器（BTB）。分支信息包括：分支类型，指示分支表示针对毫微米子例程的毫米条目（中心）指令，以及与中心指令相关联的指令长度代码（ILC）。该系统还包括执行方法的搜索逻辑。该方法包括将BTB中的分支地址定位为针对毫秒子程序的中心指令，以及根据中心指令和ILC的指令地址确定返回地址以从millicode子程序返回。该系统还包括指令获取控制以获取与搜索逻辑异步的毫微数子程序的指令。搜索逻辑也可以相对于指令解码单元进行异步操作。

4. 发明授权

US07822954B2 Methods, systems, and computer program products for recovering from branch prediction latency 有权
标题翻译：从分支预测延迟中恢复的方法，系统和计算机程序产品
公开(公告)号：US07822954B2
公开(公告)日：2010-10-26
申请号：US12034112
申请日：2008-02-20
申请人： John W. Ward, III , Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
发明人： John W. Ward, III , Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/383 , G06F9/3802 , G06F9/3861
摘要： A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started.
摘要翻译：分支预测算法用于生成是否采用分支的预测。取出一个或多个指令，使得对于每个获取的指令，预测启动在分支的预测目标处的指令的获取。执行测试以确定预测是否相对于获取的指令生成较晚，使得如果稍后检测到该分支被误预测，则该检测可以与后期预测相关。当预测相对于所获取的指令生成较晚时，通过利用由潜在预测发起的提取来选择潜在预测，使得新的获取不被开始。

5. 发明申请

US20090210684A1 METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR RECOVERING FROM BRANCH PREDICTION LATENCY 有权
标题翻译：从分支预测延迟恢复的方法，系统和计算机程序产品
公开(公告)号：US20090210684A1
公开(公告)日：2009-08-20
申请号：US12034112
申请日：2008-02-20
申请人： John W. Ward, III , Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
发明人： John W. Ward, III , Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3802 , G06F9/3861
摘要： A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started.
摘要翻译：分支预测算法用于生成是否采用分支的预测。取出一个或多个指令，使得对于每个获取的指令，预测启动在分支的预测目标处的指令的获取。执行测试以确定预测是否相对于获取的指令生成较晚，使得如果稍后检测到该分支被误预测，则该检测可以与后期预测相关。当预测相对于所获取的指令生成较晚时，通过利用由潜在预测发起的提取来选择潜在预测，使得新的获取不被开始。

6. 发明授权

US09152424B2 Mitigating instruction prediction latency with independently filtered presence predictors 有权
标题翻译：用独立过滤的存在预测器缓解指令预测延迟
公开(公告)号：US09152424B2
公开(公告)日：2015-10-06
申请号：US13523784
申请日：2012-06-14
申请人： James J. Bonanno , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
发明人： James J. Bonanno , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/38 , G06F9/3806 , G06F9/3848
摘要： Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters. The stall determination logic is configured to generate a combined indication that will stall instruction delivery, allowing potentially latent instruction predictions to be accounted for, based upon one or more non-blocked indications received from the plurality of dynamic filters.
摘要翻译：本公开的实施例包括使用耦合到处理器管线的独立滤波的指令预测存在预测器来减轻指令预测等待时间。预测存在预测器包括多个存在预测器，其被配置为并行地接收指令地址并且生成相关联的指令预测的未过滤的指示。预测存在预测器包括多个动态滤波器，每个动态滤波器耦合到多个存在预测器之一。每个动态过滤器被配置为基于其耦合到的存在预测器的性能来阻止未过滤的指示。预测存在预测器还包括耦合到多个动态滤波器的失速确定逻辑。停止确定逻辑被配置为基于从多个动态过滤器接收的一个或多个非阻塞指示来生成将停止指令传递的允许潜在潜在指令预测的组合指示。

7. 发明授权

US09135012B2 Instruction filtering 有权
标题翻译：指令过滤
公开(公告)号：US09135012B2
公开(公告)日：2015-09-15
申请号：US13523170
申请日：2012-06-14
申请人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
发明人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3844 , G06F9/30 , G06F9/30047 , G06F9/3005 , G06F9/3806 , G06F9/3836
摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.
摘要翻译：实施例涉及指令过滤。一个方面包括用于指令过滤的系统。该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。基于标记的指令文本来防止跟踪指令逻辑块的动作。

8. 发明申请

US20130339692A1 MITIGATING INSTRUCTION PREDICTION LATENCY WITH INDEPENDENTLY FILTERED PRESENCE PREDICTORS 有权
标题翻译：与独立过滤的预测者进行预防指示预测失效
公开(公告)号：US20130339692A1
公开(公告)日：2013-12-19
申请号：US13523784
申请日：2012-06-14
申请人： James J. Bonanno , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
发明人： James J. Bonanno , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/38 , G06F9/3806 , G06F9/3848
摘要： Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters. The stall determination logic is configured to generate a combined indication that will stall instruction delivery, allowing potentially latent instruction predictions to be accounted for, based upon one or more non-blocked indications received from the plurality of dynamic filters.
摘要翻译：本公开的实施例包括使用耦合到处理器管线的独立滤波的指令预测存在预测器来减轻指令预测等待时间。预测存在预测器包括多个存在预测器，其被配置为并行地接收指令地址并且生成相关联的指令预测的未过滤的指示。预测存在预测器包括多个动态滤波器，每个动态滤波器耦合到多个存在预测器之一。每个动态过滤器被配置为基于其耦合到的存在预测器的性能来阻止未过滤的指示。预测存在预测器还包括耦合到多个动态滤波器的失速确定逻辑。停止确定逻辑被配置为基于从多个动态过滤器接收的一个或多个非阻塞指示来生成将停止指令传递的允许潜在潜在指令预测的组合指示。

9. 发明申请

US20130332713A1 FAST INDEX TREE FOR ACCELERATED BRANCH PREDICTION 有权
标题翻译：快速指数树用于加速分支预测
公开(公告)号：US20130332713A1
公开(公告)日：2013-12-12
申请号：US13494443
申请日：2012-06-12
申请人： James J. Bonanno , Brian R. Prasky , Anthony Saporito
发明人： James J. Bonanno , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3844
摘要： Embodiments relate to using a fast index tree for accelerated branch prediction. A system includes a branch target buffer, a FIT structure, and a processing circuit configured to perform a method. The method includes determining that searching of the branch target buffer is to be performed under FIT control. A current search address for searching of the branch target buffer is saved. The branch target buffer is searched at the saved current search address for a branch prediction. A FIT next-search address is determined based on reading branch taken and branch not taken paths for a next search level of predicted branches from the FIT structure. The searching of the branch target buffer is re-indexed based on the FIT next-search address. It is determined whether the searching at the saved current search address located the branch prediction.
摘要翻译：实施例涉及使用用于加速分支预测的快速索引树。系统包括分支目标缓冲器，FIT结构以及被配置为执行方法的处理电路。该方法包括确定在FIT控制下执行分支目标缓冲器的搜索。保存用于搜索分支目标缓冲器的当前搜索地址。在保存的当前搜索地址搜索分支目标缓冲区以进行分支预测。基于读取从FIT结构预测分支的下一个搜索水平的分支取出和分支未采用的路径来确定FIT下一搜索地址。基于FIT下一搜索地址重新索引分支目标缓冲区的搜索。确定在保存的当前搜索地址处的搜索是否位于分支预测。

10. 发明申请

US20090217002A1 SYSTEM AND METHOD FOR PROVIDING ASYNCHRONOUS DYNAMIC MILLICODE ENTRY PREDICTION 失效
标题翻译：用于提供异步动态MILLICODE入侵预测的系统和方法
公开(公告)号：US20090217002A1
公开(公告)日：2009-08-27
申请号：US12035109
申请日：2008-02-21
申请人： James J. Bonanno , Brian R. Prasky , John G. Rell, JR. , Anthony Saporito , Chung-Lung Kevin Shum
发明人： James J. Bonanno , Brian R. Prasky , John G. Rell, JR. , Anthony Saporito , Chung-Lung Kevin Shum
IPC分类号： G06F9/312
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/30174 , G06F9/3806
摘要： A system and method for asynchronous dynamic millicode entry prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information. The branch information includes: a branch type indicating that the branch represents a millicode entry (mcentry) instruction targeting a millicode subroutine, and an instruction length code (ILC) associated with the mcentry instruction. The system also includes search logic to perform a method. The method includes locating a branch address in the BTB for the mcentry instruction targeting the millicode subroutine, and determining a return address to return from the millicode subroutine as a function of the an instruction address of the mcentry instruction and the ILC. The system further includes instruction fetch controls to fetch instructions of the millicode subroutine asynchronous to the search logic. The search logic may also operate asynchronous with respect to an instruction decode unit.
摘要翻译：提供了一种用于在处理器中进行异步动态毫代码入口预测的系统和方法。该系统包括用于保存分支信息的分支目标缓冲器（BTB）。分支信息包括：分支类型，指示分支表示针对毫微米子例程的毫米条目（中心）指令，以及与中心指令相关联的指令长度代码（ILC）。该系统还包括执行方法的搜索逻辑。该方法包括将BTB中的分支地址定位到针对毫秒子程序的中心指令，以及根据中心指令和ILC的指令地址确定返回地址，以从millicode子程序返回。该系统还包括指令获取控制以获取与搜索逻辑异步的毫微数子程序的指令。搜索逻辑也可以相对于指令解码单元进行异步操作。

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