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1. 发明授权

US08694759B2 Generating predicted branch target address from two entries storing portions of target address based on static/dynamic indicator of branch instruction type 有权
标题翻译：基于分支指令类型的静态/动态指示符，从存储部分目标地址的两个条目生成预测分支目标地址
公开(公告)号：US08694759B2
公开(公告)日：2014-04-08
申请号：US12945732
申请日：2010-11-12
申请人： James D. Dundas , Marvin A. Denman
发明人： James D. Dundas , Marvin A. Denman
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3808
摘要： A method and apparatus to utilize a branch prediction scheme that limits the expenditure of power and the area consumed caused by branch prediction schemes is provided. The method includes accessing a first entry and a second entry of the data structure, wherein each entry stores a portion of a predicted target address, determining the predicted target address using the portion of the predicted target address stored in the first entry and a portion of a branch address of a fetched branch instruction for a fetched branch instruction of a first type, and determining the predicted target address using the portion of the predicted target address stored in the first entry and the portion of the predicted target address stored in the second entry for a fetched branch instruction of a second type.
摘要翻译：提供了一种利用分支预测方案的方法和装置，其限制了功率消耗和由分支预测方案引起的消耗的面积。该方法包括访问数据结构的第一条目和第二条目，其中每个条目存储预测目标地址的一部分，使用存储在第一条目中的预测目标地址的部分确定预测目标地址，用于获取的第一类型的分支指令的获取分支指令的分支地址，以及使用存储在第一条目中的预测目标地址的部分和存储在第二条目中的预测目标地址的部分来确定预测目标地址对于第二类型的获取的分支指令。

2. 发明申请

US20120124347A1 BRANCH PREDICTION SCHEME UTILIZING PARTIAL-SIZED TARGETS 有权
标题翻译：分支预测方案利用部分大小的目标
公开(公告)号：US20120124347A1
公开(公告)日：2012-05-17
申请号：US12945732
申请日：2010-11-12
申请人： James D. Dundas , Marvin A. Denman
发明人： James D. Dundas , Marvin A. Denman
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3808
摘要： A method and apparatus to utilize a branch prediction scheme that limits the expenditure of power and the area consumed caused by branch prediction schemes is provided. The method includes accessing a first entry and a second entry of the data structure, wherein each entry stores a portion of a predicted target address, determining the predicted target address using the portion of the predicted target address stored in the first entry and a portion of a branch address of a fetched branch instruction for a fetched branch instruction of a first type, and determining the predicted target address using the portion of the predicted target address stored in the first entry and the portion of the predicted target address stored in the second entry for a fetched branch instruction of a second type.
摘要翻译：提供了一种利用分支预测方案的方法和装置，其限制了功率消耗和由分支预测方案引起的消耗的面积。该方法包括访问数据结构的第一条目和第二条目，其中每个条目存储预测目标地址的一部分，使用存储在第一条目中的预测目标地址的部分确定预测目标地址，用于获取的第一类型的分支指令的获取分支指令的分支地址，以及使用存储在第一条目中的预测目标地址的部分和存储在第二条目中的预测目标地址的部分来确定预测目标地址对于第二类型的获取的分支指令。

3. 发明授权

US09489203B2 Pre-fetching instructions using predicted branch target addresses 有权
标题翻译：使用预测的分支目标地址预取指令
公开(公告)号：US09489203B2
公开(公告)日：2016-11-08
申请号：US13711403
申请日：2012-12-11
申请人： James D. Dundas
发明人： James D. Dundas
IPC分类号： G06F9/00 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3804 , G06F9/3806 , G06F12/0862
摘要： The present application describes a method and apparatus for prefetching instructions based on predicted branch target addresses. Some embodiments of the method include providing a second cache line to a second cache when a target address for a branch instruction in a first cache line of a first cache is included in the second cache line of the first cache and when the second cache line is not resident in the second cache.
摘要翻译：本申请描述了一种基于预测的分支目标地址来预取指令的方法和装置。当第一高速缓存的第一高速缓存行中的分支指令的目标地址被包括在第一高速缓存的第二高速缓存行中时，并且当第二高速缓存行是第二高速缓存行时，该方法的一些实施例包括向第二高速缓存提供第二高速缓存行不驻留在第二个缓存中。

4. 发明申请

US20140059283A1 CONTROLLING A MEMORY ARRAY 审中-公开
标题翻译：控制内存阵列
公开(公告)号：US20140059283A1
公开(公告)日：2014-02-27
申请号：US13593343
申请日：2012-08-23
申请人： James D. Dundas
发明人： James D. Dundas
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Methods and systems for controlling a memory array are provided. A method of controlling a memory array includes: providing a next index to be read that indicates a location in the memory array from which to retrieve an output; reading validity information from a validity memory unit; comparing the next index with a last read index stored in an index memory unit; reading the output from an output memory unit when the last read index is the same as the next index and the validity information indicates the output in the output memory unit is valid; and reducing power to the memory array when the output is read from the output memory unit.
摘要翻译：提供了用于控制存储器阵列的方法和系统。一种控制存储器阵列的方法包括：提供下一个要读取的索引，该索引指示存储器阵列中从哪个检索输出的位置; 从有效性存储单元读取有效性信息; 将下一个索引与存储在索引存储器单元中的最后读取索引进行比较; 当最后一个读取索引与下一个索引相同时，读取输出存储器单元的输出，并且有效信息指示输出存储器单元中的输出有效; 并且当从输出存储器单元读取输出时，降低存储器阵列的功率。

5. 发明申请

US20100064123A1 HYBRID BRANCH PREDICTION DEVICE WITH SPARSE AND DENSE PREDICTION CACHES 有权
标题翻译：混合分支预测装置，具有稀疏和深度预测速度
公开(公告)号：US20100064123A1
公开(公告)日：2010-03-11
申请号：US12205429
申请日：2008-09-05
申请人： Gerald D. Zuraski, JR. , James D. Dundas , Anthony X. Jarvis
发明人： Gerald D. Zuraski, JR. , James D. Dundas , Anthony X. Jarvis
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A system and method for branch prediction in a microprocessor. A hybrid device stores branch prediction information in a sparse cache for no more than a common smaller number of branches within each entry of the instruction cache. For the less common case wherein an i-cache line comprises additional branches, the device stores the corresponding branch prediction information in a dense cache. Each entry of the sparse cache stores a bit vector indicating whether or not a corresponding instruction cache line includes additional branch instructions. This indication may also be used to select an entry in the dense cache for storage. A second sparse cache stores entire evicted entries from the first sparse cache.
摘要翻译：一种用于微处理器中分支预测的系统和方法。混合设备将稀疏高速缓存中的分支预测信息存储在指令高速缓存的每个条目内不超过公共较小数量的分支。对于i-cache行包括附加分支的较不常见的情况，该设备将相应的分支预测信息存储在密集高速缓存中。稀疏高速缓存的每个条目存储指示对应的指令高速缓存行是否包括附加分支指令的位向量。此指示也可用于选择密集缓存中的条目以进行存储。第二个稀疏缓存存储从第一个稀疏高速缓存中的所有被驱逐的条目。

6. 发明申请

US20110093658A1 CLASSIFYING AND SEGREGATING BRANCH TARGETS 审中-公开
标题翻译：分类和分散分支目标
公开(公告)号：US20110093658A1
公开(公告)日：2011-04-21
申请号：US12581878
申请日：2009-10-19
申请人： Gerald D. Zuraski, JR. , James D. Dundas , Anthony X. Jarvis
发明人： Gerald D. Zuraski, JR. , James D. Dundas , Anthony X. Jarvis
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A system and method for branch prediction in a microprocessor. A branch prediction unit stores an indication of a location of a branch target instruction relative to its corresponding branch instruction. For example, a target instruction may be located within a first region of memory as a branch instruction. Alternatively, the target instruction may be located outside the first region, but within a larger second region. The prediction unit comprises a branch target array corresponding to each region. Each array stores a bit range of a branch target address, wherein the stored bit range is based upon the location of the target instruction relative to the branch instruction. The prediction unit constructs a predicted branch target address by concatenating a bits stored in the branch target arrays.
摘要翻译：一种用于微处理器中分支预测的系统和方法。分支预测单元相对于其相应的分支指令存储分支目标指令的位置的指示。例如，目标指令可以作为分支指令位于存储器的第一区域内。或者，目标指令可以位于第一区域的外部，但在较大的第二区域内。预测单元包括对应于每个区域的分支目标阵列。每个阵列存储分支目标地址的比特范围，其中存储的比特范围基于目标指令相对于分支指令的位置。预测单元通过连接存储在分支目标数组中的比特来构建预测分支目标地址。

7. 发明授权

US08181005B2 Hybrid branch prediction device with sparse and dense prediction caches 有权
标题翻译：具有稀疏密集预测缓存的混合分支预测装置
公开(公告)号：US08181005B2
公开(公告)日：2012-05-15
申请号：US12205429
申请日：2008-09-05
申请人： Gerald D. Zuraski, Jr. , James D. Dundas , Anthony X. Jarvis
发明人： Gerald D. Zuraski, Jr. , James D. Dundas , Anthony X. Jarvis
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/3806
摘要： A system and method for branch prediction in a microprocessor. A hybrid device stores branch prediction information in a sparse cache for no more than a common smaller number of branches within each entry of the instruction cache. For the less common case wherein an i-cache line comprises additional branches, the device stores the corresponding branch prediction information in a dense cache. Each entry of the sparse cache stores a bit vector indicating whether or not a corresponding instruction cache line includes additional branch instructions. This indication may also be used to select an entry in the dense cache for storage. A second sparse cache stores entire evicted entries from the first sparse cache.
摘要翻译：一种用于微处理器中分支预测的系统和方法。混合设备将稀疏高速缓存中的分支预测信息存储在指令高速缓存的每个条目内不超过公共较小数量的分支。对于i-cache行包括附加分支的较不常见的情况，该设备将相应的分支预测信息存储在密集高速缓存中。稀疏高速缓存的每个条目存储指示对应的指令高速缓存行是否包括附加分支指令的位向量。此指示也可用于选择密集缓存中的条目以进行存储。第二个稀疏缓存存储从第一个稀疏高速缓存中的所有被驱逐的条目。

8. 发明授权

US06883086B2 Repair of mis-predicted load values 失效
标题翻译：修复误预测的负载值
公开(公告)号：US06883086B2
公开(公告)日：2005-04-19
申请号：US10091825
申请日：2002-03-06
申请人： James D. Dundas
发明人： James D. Dundas
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/383 , G06F9/3832 , G06F9/3842 , G06F9/3861
摘要： When fetching a load value for a load instruction results in a cache miss, the load instruction and any load-dependent instructions may be speculatively executed with a predicted load value and retired before the missing cache line is retrieved and the actual load value is determined. By storing the predicted load value in a table, when the actual load value is determined it may be compared with the predicted load value from the table. If the predicted load value was incorrect, the load and load-dependent instructions may be re-executed with the actual load value. A compiler may determine which load instructions are highly predictable and likely to result in cache misses, and designate only those load instructions for speculative execution.
摘要翻译：当读取加载指令的加载值导致高速缓存未命中时，加载指令和任何依赖于负载的指令可以用预测的负载值推测地执行，并且在检索到缺失的高速缓存行之前退出并确定实际的负载值。通过将预测负载值存储在表中，当确定实际负载值时，可以将其与来自表的预测负载值进行比较。如果预测的负载值不正确，可以用实际负载值重新执行负载和负载相关的指令。编译器可以确定哪些加载指令是高度可预测的并且可能导致高速缓存未命中，并且仅指定用于推测执行的加载指令。

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