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1. 发明申请

US20060046406A1 Programming, erasing, and reading structure for an NVM cell 有权
标题翻译： NVM单元的编程，擦除和读取结构
公开(公告)号：US20060046406A1
公开(公告)日：2006-03-02
申请号：US10930892
申请日：2004-08-31
申请人： Gowrishankar Chindalore , James Burnett , Craig Swift , Ramachandran Muralidhar
发明人： Gowrishankar Chindalore , James Burnett , Craig Swift , Ramachandran Muralidhar
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L29/1608 , H01L29/267 , H01L29/66833 , H01L29/7881
摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being more difficult to generate electron/hole pairs by impact ionization. Thus, it can be advantageous to use the SiC region for the drain during a read. The SiGe is used as the drain for programming and erase. The SiGe, having a smaller bandgap than the silicon substrate results in improved programming by generating electron/hole pairs by impact ionization and improved erasing by generating electron hole/pairs by band-to-band tunneling, both at lower voltage levels.
摘要翻译：非易失性存储器（NVM）具有硅锗（SiGe）漏极和硅碳（SiC）源。作为SiC的源提供通道上的应力，其改善N沟道迁移率。 SiC也具有比衬底更大的带隙，这是硅。这导致通过冲击电离产生电子/空穴对更困难。因此，在读取期间使用SiC区域用于漏极是有利的。 SiGe用作编程和擦除的漏极。具有比硅衬底更小的带隙的SiGe通过在较低电压电平下通过产生电子/空穴对的冲击电离和通过频带隧穿产生电子空穴/对来改善擦除来改善编程。

2. 发明申请

US20060043482A1 Programming and erasing structure for an NVM cell 有权
公开(公告)号：US20060043482A1
公开(公告)日：2006-03-02
申请号：US10930891
申请日：2004-08-31
申请人： James Burnett , Gowrishankar Chindalore , Craig Swift , Ramachandran Muralidhar
发明人： James Burnett , Gowrishankar Chindalore , Craig Swift , Ramachandran Muralidhar
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/7881 , H01L29/7885
摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the cavity with an increasing doping level. Thus, the PN junction between the substrate and the drain is lightly doped on both the P and N side. The drain progressively becomes more heavily doped until the maximum desired doping level is reached, and the remaining portion of the SiGe drain is doped at this maximum desired level. As a further enhancement, the perimeter of the SiGe in the substrate is the same conductivity type as that of the substrate and channel. Thus a portion of the channel is in the SiGe.

3. 发明申请

US20060186456A1 NVM cell on SOI and method of manufacture 审中-公开
标题翻译： NVM单元在SOI及其制造方法
公开(公告)号：US20060186456A1
公开(公告)日：2006-08-24
申请号：US11060996
申请日：2005-02-18
申请人： James Burnett , Ramachandran Muralidhar
发明人： James Burnett , Ramachandran Muralidhar
IPC分类号： H01L29/788
CPC分类号： G11C16/0416 , H01L21/26586 , H01L27/115 , H01L27/11521 , H01L29/1083 , H01L29/7881
摘要： A non-volatile memory (NVM) device formed in a semiconductor-on-insulator (SOI) substrate has a trap region on the source side only to speed up the process of programming. During programming of an NVM device in partially depleted SOI, holes are generated that slow down the formation of electrons hot enough to jump to the storage layer of the NVM. To reduce this effect, the trap region is formed below the lightly-doped portion of the source region and preferably extends to an area under the gate on the source side. This can be achieved using an angled implant of a neutral impurity, such as xenon, argon, or germanium, while masking the drain side. The trap region thus extends under the gate on the source side to recombine with holes that are generated during programming. The trap region also extends to contact the source.
摘要翻译：形成在绝缘体上半导体（SOI））衬底中的非易失性存储器（NVM）器件在源极上具有陷阱区域，仅用于加速编程过程。在部分耗尽的SOI中的NVM器件的编程期间，产生空穴，其减慢热到足以跳到NVM的存储层的电子的形成。为了减小这种影响，陷波区域形成在源极区域的轻掺杂部分下方，优选地延伸到源极侧的栅极下方的区域。这可以使用中性杂质（例如氙，氩或锗）的倾斜注入来实现，同时掩蔽漏极侧。陷阱区域因此在源极侧的栅极下方与编程期间产生的孔重新组合。陷阱区域也延伸以接触源。

4. 发明申请

US20060186457A1 Methods for programming a floating body nonvolatile memory 有权
标题翻译：用于编程浮体非易失性存储器的方法
公开(公告)号：US20060186457A1
公开(公告)日：2006-08-24
申请号：US11061005
申请日：2005-02-18
申请人： James Burnett , Ramachandran Muralidhar
发明人： James Burnett , Ramachandran Muralidhar
IPC分类号： H01L29/788
CPC分类号： H01L21/26586 , H01L27/115 , H01L27/11521 , H01L29/1083 , H01L29/7881
摘要： A technique to speed up the programming of a non-volatile memory device that has a floating body actively removes holes from the floating body that have accumulated after performing hot carrier injection (HCI). The steps of HCI and active hole removal can be alternated until the programming is complete. The active hole removal is faster than passively allowing holes to be removed, which can take milliseconds. The active hole removal can be achieved by reducing the drain voltage to a negative voltage and reducing the gate voltage as well. This results in directly withdrawing the holes from the floating body to the drain. Alternatively, reducing the drain voltage while maintaining current flow stops impact ionization while sub channel current collects the holes. Further alternatively, applying a negative gate voltage causes electrons generated by band to band tunneling and impact ionization near the drain to recombine with holes.
摘要翻译：一种用于加速具有浮体的非易失性存储装置的编程的技术主动地从执行热载流子注入（HCI）之后累积的浮体中去除空穴。 HCI和有源孔去除的步骤可以交替，直到编程完成。有源孔移除比被动地更快地允许孔被去除，这可能需要几毫秒。有源孔去除可以通过将漏极电压降低到负电压并降低栅极电压来实现。这导致从浮体直接排出孔到排水管。或者，在保持电流的同时降低漏极电压停止冲击电离，而子通道电流收集孔。或者，施加负栅极电压使得通过带状隧穿产生的电子和靠近漏极的冲击电离与空穴重新组合。

5. 发明申请

US20070158764A1 Electronic device including a fin-type transistor structure and a process for forming the electronic device 有权
标题翻译：包括鳍型晶体管结构的电子器件和用于形成电子器件的工艺
公开(公告)号：US20070158764A1
公开(公告)日：2007-07-12
申请号：US11328594
申请日：2006-01-10
申请人： Marius Orlowski , James Burnett
发明人： Marius Orlowski , James Burnett
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.
摘要翻译：电子器件可以包括绝缘层和鳍型晶体管结构。翅片型结构可以具有彼此间隔开的半导体翅片和栅电极。电介质层和间隔结构可以位于半导体鳍片和栅电极之间。半导体鳍片可以包括沟道区域，该沟道区域包括与相对较低V T T T相关的部分与绝缘层之间相对较高的V SUB相关联的部分。在一个实施例中，电源电压低于沟道区的相对较高的V SUB。还公开了一种用于形成电子器件的工艺。

6. 发明申请

US20070112049A1 Small Molecule Inhibitors of Botulinum Neurotoxins 失效
标题翻译：肉毒杆菌神经毒素的小分子抑制剂
公开(公告)号：US20070112049A1
公开(公告)日：2007-05-17
申请号：US11464007
申请日：2006-08-11
申请人： Sina Bavari , Rick Gussio , James Burnett
发明人： Sina Bavari , Rick Gussio , James Burnett
IPC分类号： A61K31/427 , A61K31/423 , A61K31/4184
CPC分类号： A61K31/4184 , A61K31/423 , A61K31/427 , A61K31/428 , C07D209/10 , C07D209/12 , C07D209/14 , C07D333/56 , C07D333/60 , C07D401/06 , C07D401/12 , C07D403/04 , C07D405/06 , C07D405/14 , C07D407/06 , C07D409/04 , Y02A50/406 , Y02A50/473
摘要： Disclosed herein are methods of inhibiting the activity of Botulinum neurotoxin A metalloprotease with the compounds disclosed herein. Also disclosed are methods of treating, inhibiting or preventing intoxication caused by bacteria of at least one bacterial strain in a subject, and pharmaceutical and cosmetic compositions comprising the compounds disclosed herein.
摘要翻译：本文公开的是使用本文公开的化合物抑制肉毒杆菌神经毒素A金属蛋白酶的活性的方法。还公开了治疗，抑制或预防受试者中至少一种细菌菌株的细菌引起的中毒的方法，以及包含本文公开的化合物的药物和化妆品组合物。

7. 发明申请

US20050156229A1 Integrated circuit device and method therefor 审中-公开
公开(公告)号：US20050156229A1
公开(公告)日：2005-07-21
申请号：US11014661
申请日：2004-12-16
申请人： Geoffrey Yeap , Srinivas Jallepalli , Yongjoo Jeon , James Burnett , Rana Singh , Paul Grudowski
发明人： Geoffrey Yeap , Srinivas Jallepalli , Yongjoo Jeon , James Burnett , Rana Singh , Paul Grudowski
IPC分类号： H01L21/336 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L29/76 , H01L29/78
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/11541 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

8. 发明申请

US20050153945A1 Small molecules and a pharmacophore model for inhibition of botulinum toxin and methods of making and using thereof 失效
标题翻译：用于抑制肉毒杆菌毒素的小分子和药效团模型及其制备和使用方法
公开(公告)号：US20050153945A1
公开(公告)日：2005-07-14
申请号：US10935622
申请日：2004-09-08
申请人： Sina Bavari , James Schmidt , James Burnett , Rick Gussio
发明人： Sina Bavari , James Schmidt , James Burnett , Rick Gussio
IPC分类号： A61K31/4709 , A61K31/473 , A61K31/555 , A61K31/63 , C07K20060101 , G01N33/48 , G01N33/50 , G01N33/53 , G06F19/00
CPC分类号： A61K31/635 , A61K31/47 , A61K31/4706 , A61K45/06 , G06F19/705 , G06F19/706 , A61K2300/00
摘要： Disclosed herein is a pharmacophore model for inhibiting Botulinum neurotoxin A metalloprotease activity which comprises a first plane A, a second plane B, a first hydrophobic moiety C, a second hydrophobic moiety D and a positive ionizable substituent E. The pharmacophore model may further comprise a heteroatom in the first plane A. In some embodiments, the distance between the center of the first plane A and the center of the second plane B is about 6.5 to about 9.5 Å. In some embodiments, the distance between the center of the first hydrophobic moiety C and the center of the second hydrophobic moiety D is about 8.0 to about 16.0 Å. In some embodiments, the distance between the center of the first plane to the center of the first hydrophobic moiety C is about 3.0 to about 5.0 Å. In some embodiments, the distance between the center of the second plane to the center of the second hydrophobic moiety C is about 3.0 to about 5.0 Å. In some embodiments, the distance between the center of the first plane to the center of the positive ionizable substituent is about 6.5 to about 9.5 Å.
摘要翻译：本文公开了用于抑制肉毒杆菌神经毒素A金属蛋白酶活性的药效团模型，其包含第一平面A，第二平面B，第一疏水部分C，第二疏水部分D和可阳离子化取代基E.药效基团模型还可包含在一些实施例中，第一平面A的中心与第二平面B的中心之间的距离为约6.5至约9.5。在一些实施方案中，第一疏水部分C的中心与第二疏水部分D的中心之间的距离为约8.0至约16.0。在一些实施方案中，第一平面的中心与第一疏水部分C的中心之间的距离为约3.0至约5.0。在一些实施方案中，第二平面的中心与第二疏水部分C的中心之间的距离为约3.0至约5.0。在一些实施方案中，第一平面的中心与正电离取代基的中心之间的距离为约6.5至约9.5。

9. 发明申请

US20070211526A1 Switch device and method 有权
标题翻译：开关装置及方法
公开(公告)号：US20070211526A1
公开(公告)日：2007-09-13
申请号：US11373532
申请日：2006-03-10
申请人： James Burnett
发明人： James Burnett
IPC分类号： G11C11/34 , G11C11/00
CPC分类号： G11C11/413 , G11C7/02 , H01L27/11 , H01L27/1104 , H01L29/66795 , H01L29/785
摘要： A device is disclosed having a first Field Effect Transistor having a channel region controlled by a gate, a second Field Effect Transistor having a first channel region substantially controlled by a first gate, and a second channel region substantially controlled by a second gate. The gate of the first Field Effect Transistor and the first gate of the second Field Effect Transistor are coupled to a memory write line. The second gate of the second Field Effect Transistor receives a control signal from a memory bit cell.
摘要翻译：公开了一种具有第一场效应晶体管的器件，其具有由栅极控制的沟道区域，第二场效应晶体管具有基本由第一栅极控制的第一沟道区域和由第二栅极基本控制的第二沟道区域。第一场效应晶体管的栅极和第二场效应晶体管的第一栅极耦合到存储器写入线。第二场效应晶体管的第二栅极从存储器位单元接收控制信号。

10. 发明申请

US20070093054A1 Multiple device types including an inverted-T channel transistor and method therefor 有权
标题翻译：多种器件类型，包括反向T沟道晶体管及其方法
公开(公告)号：US20070093054A1
公开(公告)日：2007-04-26
申请号：US11257972
申请日：2005-10-25
申请人： Byoung Min , James Burnett , Leo Mathew
发明人： Byoung Min , James Burnett , Leo Mathew
IPC分类号： H01L21/4763 , H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L27/1104 , H01L21/823431 , H01L27/11 , H01L29/66795 , H01L29/785
摘要： A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.
摘要翻译：提供一种制造半导体器件的方法。该方法包括形成具有在垂直有源区两侧延伸的垂直有源区和水平有源区的第一晶体管。该方法还包括形成具有垂直有源区的第二晶体管。该方法还包括形成具有垂直有源区和仅在垂直有源区的一侧上延伸的水平有源区的第三晶体管。

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