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1. 发明申请

US20050269695A1 Surface-mount chip-scale package 审中-公开
标题翻译：表面贴装芯片级封装
公开(公告)号：US20050269695A1
公开(公告)日：2005-12-08
申请号：US10862710
申请日：2004-06-07
申请人： James Brogle , Timothy Boles , Joel Goodrich
发明人： James Brogle , Timothy Boles , Joel Goodrich
IPC分类号： H01L23/14 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/02 , H01L27/08 , H01L23/52
CPC分类号： H01L27/0248 , H01L27/0814 , H01L2224/16 , H01L2924/12032 , H01L2924/1301 , H01L2924/00
摘要： A chip-scale package and method of manufacturing a chip-scale package are provided. The chip-scale package includes a mounting portion defined by a plurality of metal layers formed on each of a plurality of semiconductor regions for mounting a device thereto. The mounting portions are formed on a first side of the plurality of semiconductor regions. The chip-scale package further includes a backside metal surface formed on each of a second side of the plurality of semiconductor regions, with the plurality of semiconductor regions providing electrical connection between the mounting portions and the backside metal surfaces.
摘要翻译：提供了芯片级封装和芯片级封装的制造方法。芯片级封装包括由形成在多个半导体区域中的每一个上的多个金属层限定的用于安装器件的安装部分。安装部分形成在多个半导体区域的第一侧上。芯片级封装还包括形成在多个半导体区域的第二侧上的每个上的背面金属表面，多个半导体区域在安装部分和背面金属表面之间提供电连接。

2. 发明申请

US20050006729A1 Method of making heterojunction P-I-N diode 有权
标题翻译：异质结P-I-N二极管的制造方法
公开(公告)号：US20050006729A1
公开(公告)日：2005-01-13
申请号：US10915579
申请日：2004-08-10
申请人： David Hoag , Timothy Boles , James Brogle
发明人： David Hoag , Timothy Boles , James Brogle
IPC分类号： H01L29/861 , H01L29/868 , H01L31/075
CPC分类号： H01L29/868
摘要： A heterojunction P—I—N diode switch comprises a first layer of doped semiconductor material of a first doping type, a second layer of doped semiconductor material of a second doping type and a substrate on which is disposed the first and second layers. An intrinsic layer of semiconductor material is disposed between the first layer and second layer. The semiconductor material composition of at least one of the first layer and second layer is sufficiently different from that of the intrinsic layer so as to form a heterojunction therebetween, creating an energy barrier in which injected carriers from the junction are confined by the barrier, effectively reducing the series resistance within the I region of the P—I—N diode and the insertion loss relative to that of homojunction P—I—N diodes.
摘要翻译：异质结P-I-N二极管开关包括第一掺杂类型的第一掺杂半导体材料层，第二掺杂类型的掺杂半导体材料的第二层和在其上设置第一和第二层的衬底。半导体材料的本征层设置在第一层和第二层之间。第一层和第二层中的至少一个的半导体材料组成与本征层的半导体材料组成充分不同，从而在它们之间形成异质结，产生能量势垒，其中来自接合处的注入的载流子被屏障限制降低PIN二极管的I区域内的串联电阻和相对于同型结PIN二极管的插入损耗。

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