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1. 发明授权

US08900008B2 Universal press-fit connection for printed circuit boards 有权
标题翻译：印刷电路板的通用压配连接
公开(公告)号：US08900008B2
公开(公告)日：2014-12-02
申请号：US13481176
申请日：2012-05-25
申请人： James A. Day, Jr. , Zachary B. Durham , Luke D. Remis , Tony C. Sass , Gregory D. Sellman
发明人： James A. Day, Jr. , Zachary B. Durham , Luke D. Remis , Tony C. Sass , Gregory D. Sellman
IPC分类号： H01R13/60
CPC分类号： H05K13/04 , H01R12/585 , H05K1/115 , H05K3/308 , H05K3/325 , H05K2201/09845 , H05K2201/1059 , H05K2201/10856 , H05K2201/10878
摘要： A universal press-fit connection allows a component having a connector pin to be connected to a compatible plated through hole of a circuit board regardless of circuit board thickness. The connector pin includes a proximate end adjacent the component, a distal end with a fork lock, and a compliant portion between the proximate and distal ends. A multi-width through hole includes a first portion partially extending through the circuit board and a second, wider portion extending beyond the first portion. The fork lock initially moves radially inward upon insertion into the first portion via flexing of the compliant portion, and re-expands when entering the second portion. The compliant portion engages the through hole and the fork lock secures the connector pin in the through hole.
摘要翻译：通用压配合连接允许具有连接器引脚的部件连接到电路板的兼容的电镀通孔，而与电路板厚度无关。连接器销包括邻近部件的近端，具有叉锁的远端以及近端和远端之间的柔顺部分。多宽度通孔包括部分延伸穿过电路板的第一部分和延伸超过第一部分的第二较宽部分。当通过柔性部分的弯曲插入到第一部分中时，叉锁首先向内径向移动，并且当进入第二部分时，叉锁重新膨胀。柔性部分接合通孔，叉锁将连接器销固定在通孔中。

2. 发明申请

US20130316551A1 UNIVERSAL PRESS-FIT CONNECTION FOR PRINTED CIRCUIT BOARDS 有权
标题翻译：用于印刷电路板的通用压力连接
公开(公告)号：US20130316551A1
公开(公告)日：2013-11-28
申请号：US13481176
申请日：2012-05-25
申请人： James A. Day, JR. , Zachary B. Durham , Luke D. Remis , Tony C. Sass , Gregory D. Sellman
发明人： James A. Day, JR. , Zachary B. Durham , Luke D. Remis , Tony C. Sass , Gregory D. Sellman
IPC分类号： H01R12/58 , H05K3/30
CPC分类号： H05K13/04 , H01R12/585 , H05K1/115 , H05K3/308 , H05K3/325 , H05K2201/09845 , H05K2201/1059 , H05K2201/10856 , H05K2201/10878
摘要： A universal press-fit connection allows a component having a connector pin to be connected to a compatible plated through hole of a circuit board regardless of circuit board thickness. The connector pin includes a proximate end adjacent the component, a distal end with a fork lock, and a compliant portion between the proximate and distal ends. A multi-width through hole includes a first portion partially extending through the circuit board and a second, wider portion extending beyond the first portion. The fork lock initially moves radially inward upon insertion into the first portion via flexing of the compliant portion, and re-expands when entering the second portion. The compliant portion engages the through hole and the fork lock secures the connector pin in the through hole.
摘要翻译：通用压配合连接允许具有连接器引脚的部件连接到电路板的兼容的电镀通孔，而与电路板厚度无关。连接器销包括邻近部件的近端，具有叉锁的远端以及近端和远端之间的柔顺部分。多宽度通孔包括部分延伸穿过电路板的第一部分和延伸超过第一部分的第二较宽部分。当通过柔性部分的弯曲插入到第一部分中时，叉锁首先向内径向移动，并且当进入第二部分时，叉锁重新膨胀。柔性部分接合通孔，叉锁将连接器销固定在通孔中。

3. 发明授权

US09917033B2 Multicomponent heat sink with movable fin support portion 有权
公开(公告)号：US09917033B2
公开(公告)日：2018-03-13
申请号：US13533376
申请日：2012-06-26
申请人： William M. Megarity, Jr. , Luke D. Remis , Gregory D. Sellman
发明人： William M. Megarity, Jr. , Luke D. Remis , Gregory D. Sellman
IPC分类号： H01L23/40
CPC分类号： H01L23/4006 , H01L2023/4081 , H01L2924/0002 , Y10T29/49826 , H01L2924/00
摘要： A heat sink comprises a base and a fin support larger in area than the base and supporting fins that may be positioned in a plurality of orientations relative to the base. The base is adapted for being connected to a heat-generating electronic component on a circuit board, and the heat sink dissipates heat generated by the heat-generating electronic device and conducted through the base and the fin support to the fins supported thereon. The heat sink dissipates heat from the heat-generating electronic device in a first operable position and in a second operable position. The heat sink may be moved from the first to the second operable position to facilitate access to electrical contacts proximal the heat-generating electronic component.

4. 发明申请

US20140071647A1 INTEGRATED CIRCUIT RETENTION MECHANISM WITH RETRACTABLE COVER 有权
标题翻译：集成电路保留机制与可复封
公开(公告)号：US20140071647A1
公开(公告)日：2014-03-13
申请号：US13610923
申请日：2012-09-12
申请人： Jeremy S. Bridges , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Jeremy S. Bridges , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： H05K7/00
CPC分类号： H05K7/1429 , H01L23/40 , H01L23/4006 , H01L2023/4056 , H01L2023/4068 , H01L2023/4087 , H01L2924/0002 , H05K7/1007 , H01L2924/00
摘要： A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site.
摘要翻译：计算机处理器保持装置包括负载框架，负载板和一对可缩回盖构件。负载框架可以固定到处理器安装位置周围的电路板。负载板枢转地联接到负载框架，并且可在打开状态之间枢转，以在处理器安装位置处接收处理器并且与接收到的处理器的外围封闭。当负载板关闭时，负载板具有对处理器安装位置开放的窗口。可缩回的盖构件跨越窗户，并且可沿轨道彼此交替移动以覆盖处理器安装位置并远离彼此以暴露处理器安装位置。

5. 发明申请

US20140013151A1 I2C MULTIPLEXER SWITCHING AS A FUNCTION OF CLOCK FREQUENCY 有权
标题翻译： I2C多路复用器切换作为时钟频率的功能
公开(公告)号：US20140013151A1
公开(公告)日：2014-01-09
申请号：US13541750
申请日：2012-07-04
申请人： Michael DeCesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
发明人： Michael DeCesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC分类号： G06F1/04 , G06F13/36
CPC分类号： G06F13/4282
摘要： In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port.
摘要翻译：根据本发明的一个实施例，可以提供用于I2C总线接口的I2C总线复用电路。 I2C总线复用电路可以通过I2C总线从I2C主器件检测启动命令，缓冲来自I2C主器件的数据，检测总线串行时钟（SCL）线的时钟频率，从而有助于I2C总线接口中的多路开关切换的I2C主器件，将I2C主器件的串行数据（SDA）线保持在时钟拉伸状态，并根据检测到的I2C主器件SCL的时钟频率选择一个端口。该方法还可以包括将所缓冲的数据发送到所选端口上的I2C从设备。该方法还可以包括从所选端口上的I2C从设备接收确认。

6. 发明授权

US08959380B2 Dynamically optimizing bus frequency of an inter-integrated circuit (‘I2C’) bus 有权
标题翻译：动态优化集成电路（“I2C”）总线的总线频率
公开(公告)号：US08959380B2
公开(公告)日：2015-02-17
申请号：US13467332
申请日：2012-05-09
申请人： Michael Decesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Michael Decesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F1/08
CPC分类号： G06F1/324 , G06F9/44 , G06F13/38 , G06F13/4282
摘要： Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.
摘要翻译：优化I2C总线频率，总线包括耦合主节点和从节点的信号线，耦合到上升时间检测电路的信号线监视信号线的电压，电压在逻辑低电平和逻辑高电平之间交替，其中优化频率包括：在信号线上升期间检测第一电压，第一电压大于逻辑低电压; 启动一个计数器，为电路的每个时钟周期增加一次; 检测信号线上的第二电压，第二电压大于第一电压并小于逻辑高电平; 停止柜台根据时钟周期和计数器值计算上升时间; 确定上升时间是否大于最大阈值; 并且如果计算的上升时间大于最大阈值，则增加I2C总线频率。

7. 发明授权

US08954634B2 Operating a demultiplexer on an inter-integrated circuit (‘I2C’) bus 有权
标题翻译：在集成电路（“I2C”）总线上操作多路分解器
公开(公告)号：US08954634B2
公开(公告)日：2015-02-10
申请号：US13530245
申请日：2012-06-22
申请人： Michael DeCesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Michael DeCesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F3/00
CPC分类号： G06F13/4291
摘要： Operating a demultiplexer on an I2C bus, the demultiplexer including a set of input signal lines from an I2C master and a plurality of sets of output signal lines, the demultiplexer configured to couple the inputs among the output in dependence upon a demultiplexer select signal line that couples the demultiplexer to a rise time detection circuit, where the rise time detection circuit is also coupled to the input signal lines and the rise time detection circuit: monitors a voltage of at least one of the input signal lines, including: receiving, from the I2C master, a signal on one of the lines; and detecting rise time of the signal; and if the rise time of the signal is less than a predefined threshold, configuring the demultiplexer to vary the coupling of the input signal lines from a first set of outputs to a second set.
摘要翻译：在I2C总线上操作解复用器，解复用器包括来自I2C主机和多组输出信号线的一组输入信号线，该多路分配器被配置为根据解复用器选择信号线在输出之间耦合输入将解复用器耦合到上升时间检测电路，其中上升时间检测电路还耦合到输入信号线和上升时间检测电路：监视至少一个输入信号线的电压，包括：从 I2C主机，其中一条信号; 并检测信号的上升时间; 并且如果信号的上升时间小于预定阈值，则配置解复用器以改变输入信号线与第一组输出到第二组的耦合。

8. 发明授权

US08909844B2 Inter-integrated circuit (I2C) multiplexer switching as a function of clock frequency 有权
标题翻译：集成电路（I2C）多路开关作为时钟频率的函数
公开(公告)号：US08909844B2
公开(公告)日：2014-12-09
申请号：US13541750
申请日：2012-07-04
申请人： Michael DeCesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
发明人： Michael DeCesaris , Luke D. Remis , Gregory D. Sellman , Steven L. Vanderlinden
IPC分类号： G06F13/00
CPC分类号： G06F13/4282
摘要： In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port.
摘要翻译：根据本发明的一个实施例，可以提供用于I2C总线接口的I2C总线复用电路。 I2C总线复用电路可以通过I2C总线从I2C主器件检测启动命令，缓冲来自I2C主器件的数据，检测总线串行时钟（SCL）线的时钟频率，从而有助于I2C总线接口中的多路开关切换的I2C主器件，将I2C主器件的串行数据（SDA）线保持在时钟拉伸状态，并根据检测到的I2C主器件SCL的时钟频率选择一个端口。该方法还可以包括将所缓冲的数据发送到所选端口上的I2C从设备。该方法还可以包括从所选端口上的I2C从设备接收确认。

9. 发明授权

US08898358B2 Multi-protocol communication on an I2C bus 有权
标题翻译： I2C总线上的多协议通信
公开(公告)号：US08898358B2
公开(公告)日：2014-11-25
申请号：US13541749
申请日：2012-07-04
申请人： Michael DeCesaris , Pravin S. Patel , Luke D. Remis , Gregory D. Sellman
发明人： Michael DeCesaris , Pravin S. Patel , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F13/42 , G06F13/40 , G06F13/38
CPC分类号： G06F13/385 , G06F13/4027 , G06F13/4282
摘要： A method, device and computer program product for providing multi-protocol communication on an inter-integrated circuit (I2C) bus. The method for providing multi-protocol communication on an inter-integrated circuit (I2C) bus can include issuing a start command by a bus management device onto the I2C bus. Thereafter, the bus management device can send an embedded differential protocol to a non-I2C device. Once communication with the non-I2C device is completed, the bus management device can issue a stop command to release the I2C bus. In one aspect of this embodiment, the method can include receiving a response from the non-I2C device.
摘要翻译：一种用于在集成电路（I2C）总线上提供多协议通信的方法，设备和计算机程序产品。在集成电路（I2C）总线上提供多协议通信的方法可以包括由总线管理装置向I2C总线发出启动命令。此后，总线管理装置可以向非I2C设备发送嵌入式差分协议。一旦与非I2C设备的通信完成，总线管理设备就可以发出停止命令来释放I2C总线。在该实施例的一个方面，该方法可以包括从非I2C设备接收响应。

10. 发明授权

US08832538B2 Detecting data transmission errors in an inter-integrated circuit (‘I2C’) system 有权
标题翻译：检测集成电路（“I2C”）系统中的数据传输错误
公开(公告)号：US08832538B2
公开(公告)日：2014-09-09
申请号：US13530318
申请日：2012-06-22
申请人： Michael Decesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Michael Decesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/098 , H04L2001/0094
摘要： Detecting data transmission errors in an I2C system that includes a source device, an destination device, and a signal line coupling the I2C source and destination device, including: receiving, by the I2C destination device from the I2C source device, a data transmission signal, the data transmission signal encoded with a set of bits; detecting, by the I2C destination device, rise time of a preselected bit in the set of bits; if the detected rise time is less than a predefined threshold, determining that the I2C source device injected a parity bit in the signal, and if the detected rise time is not less than the predefined threshold, determining that the I2C source device did not inject a parity bit in the signal; and determining whether the data transmission signal includes an error in dependence upon the parity of the set of bits.
摘要翻译：检测I2C系统中的数据传输错误，该系统包括源设备，目标设备和耦合I2C源设备和目标设备的信号线，包括：由I2C源设备从I2C源设备接收数据传输信号，数据传输信号用一组位编码; 通过I2C目的地设备检测位组中的预选位的上升时间; 如果检测到的上升时间小于预定阈值，则确定I2C源设备在信号中注入了奇偶校验位，并且如果检测到的上升时间不小于预定阈值，则确定I2C源设备未注入信号中的奇偶校验位; 以及确定所述数据传输信号是否包括与所述位组的奇偶校验有关的错误。

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