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1. 发明申请

US20140071647A1 INTEGRATED CIRCUIT RETENTION MECHANISM WITH RETRACTABLE COVER 有权
标题翻译：集成电路保留机制与可复封
公开(公告)号：US20140071647A1
公开(公告)日：2014-03-13
申请号：US13610923
申请日：2012-09-12
申请人： Jeremy S. Bridges , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Jeremy S. Bridges , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： H05K7/00
CPC分类号： H05K7/1429 , H01L23/40 , H01L23/4006 , H01L2023/4056 , H01L2023/4068 , H01L2023/4087 , H01L2924/0002 , H05K7/1007 , H01L2924/00
摘要： A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site.
摘要翻译：计算机处理器保持装置包括负载框架，负载板和一对可缩回盖构件。负载框架可以固定到处理器安装位置周围的电路板。负载板枢转地联接到负载框架，并且可在打开状态之间枢转，以在处理器安装位置处接收处理器并且与接收到的处理器的外围封闭。当负载板关闭时，负载板具有对处理器安装位置开放的窗口。可缩回的盖构件跨越窗户，并且可沿轨道彼此交替移动以覆盖处理器安装位置并远离彼此以暴露处理器安装位置。

2. 发明授权

US08902611B2 Integrated circuit retention mechanism with retractable cover 有权
标题翻译：集成电路保持机构，带可伸缩盖
公开(公告)号：US08902611B2
公开(公告)日：2014-12-02
申请号：US13610923
申请日：2012-09-12
申请人： Jeremy S. Bridges , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Jeremy S. Bridges , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： H05K7/02
CPC分类号： H05K7/1429 , H01L23/40 , H01L23/4006 , H01L2023/4056 , H01L2023/4068 , H01L2023/4087 , H01L2924/0002 , H05K7/1007 , H01L2924/00
摘要： A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site.
摘要翻译：计算机处理器保持装置包括负载框架，负载板和一对可缩回盖构件。负载框架可以固定到处理器安装位置周围的电路板。负载板枢转地联接到负载框架，并且可在打开状态之间枢转，以在处理器安装位置处接收处理器并且与接收到的处理器的外围封闭。当负载板关闭时，负载板具有对处理器安装位置开放的窗口。可缩回的盖构件跨越窗户，并且可沿轨道彼此交替移动以覆盖处理器安装位置并远离彼此以暴露处理器安装位置。

3. 发明授权

US08831772B2 Lift apparatus for stable placement of components into a rack 有权
标题翻译：用于将部件稳定放置到机架中的提升装置
公开(公告)号：US08831772B2
公开(公告)日：2014-09-09
申请号：US13557357
申请日：2012-07-25
申请人： Jeremy S. Bridges , Michael DeCesaris , Luke D. Remis , Gregory D. Sellman
发明人： Jeremy S. Bridges , Michael DeCesaris , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F7/00 , G06F17/50
CPC分类号： G11B15/68
摘要： A method uses scales onboard a lift apparatus to weigh an uninstalled component that is positioned on the lift apparatus for installation into a rack. Data is accessed that identifies the weight and rack location of components currently installed in the rack, and one or more available rack locations are identified where the component may be installed without violating one or more predetermined rack stability rules. The method then uses the lift apparatus to raise the component into a selected one of the one or more available rack locations. The components are preferably information technology components, such as servers, network switches and power distribution units.
摘要翻译：一种方法使用升降机装置上的刻度来称重位于升降机装置上的用于安装到机架中的卸载部件。访问数据，其识别当前安装在机架中的部件的重量和机架位置，并且识别可以安装部件的一个或多个可用的机架位置，而不违反一个或多个预定的机架稳定性规则。该方法然后使用提升装置将部件升高成一个或多个可用的机架位置中的选定的一个。这些组件优选地是诸如服务器，网络交换机和配电单元之类的信息技术组件。

4. 发明申请

US20140031971A1 LIFT APPARATUS FOR STABLE PLACEMENT OF COMPONENTS INTO A RACK 有权
标题翻译：用于将组件稳定放置在机架中的提升装置
公开(公告)号：US20140031971A1
公开(公告)日：2014-01-30
申请号：US13557357
申请日：2012-07-25
申请人： Jeremy S. Bridges , Michael DeCesaris , Luke D. Remis , Gregory D. Sellman
发明人： Jeremy S. Bridges , Michael DeCesaris , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F7/00
CPC分类号： G11B15/68
摘要： A method uses scales onboard a lift apparatus to weigh an uninstalled component that is positioned on the lift apparatus for installation into a rack. Data is accessed that identifies the weight and rack location of components currently installed in the rack, and one or more available rack locations are identified where the component may be installed without violating one or more predetermined rack stability rules. The method then uses the lift apparatus to raise the component into a selected one of the one or more available rack locations. The components are preferably information technology components, such as servers, network switches and power distribution units.
摘要翻译：一种方法使用升降机装置上的刻度来称重位于升降机装置上的用于安装到机架中的卸载部件。访问数据，其识别当前安装在机架中的部件的重量和机架位置，并且识别可以安装部件的一个或多个可用的机架位置，而不违反一个或多个预定的机架稳定性规则。该方法然后使用提升装置将部件升高成一个或多个可用的机架位置中的选定的一个。这些组件优选地是诸如服务器，网络交换机和配电单元之类的信息技术组件。

5. 发明授权

US08684757B2 Memory module connector with air deflection system 有权
标题翻译：带空气偏转系统的内存模块连接器
公开(公告)号：US08684757B2
公开(公告)日：2014-04-01
申请号：US13458373
申请日：2012-04-27
申请人： Jeremy S. Bridges , William M. Megarity , Luke D. Remis , Gregory D. Sellman
发明人： Jeremy S. Bridges , William M. Megarity , Luke D. Remis , Gregory D. Sellman
IPC分类号： H01R4/60
CPC分类号： G06F1/20 , H01R12/7029 , H01R12/721
摘要： In one embodiment, a memory module connector includes sidewalls extending along a length of the connector body. A longitudinally oriented socket is provided between the sidewalls for receiving a card edge of a memory module. A top of the connector defines a socket opening. A bottom of the connector is for mounting to a system board. A plurality of air deflectors is provided adjacent to the connector body to manipulate airflow to improve cooling. The size, positioning, and spacing of the air deflectors may be selected to optimize cooling.
摘要翻译：在一个实施例中，存储器模块连接器包括沿连接器主体的长度延伸的侧壁。在侧壁之间提供纵向定位的插座，用于接收存储器模块的卡边缘。连接器的顶部定义了插座开口。连接器的底部用于安装到系统板。多个空气导流器邻近连接器主体设置以操纵气流以改善冷却。可以选择空气导流板的尺寸，定位和间距以优化冷却。

6. 发明申请

US20130288502A1 MEMORY MODULE CONNECTOR WITH AIR DEFLECTION SYSTEM 有权
标题翻译：具有空气偏转系统的存储模块连接器
公开(公告)号：US20130288502A1
公开(公告)日：2013-10-31
申请号：US13458373
申请日：2012-04-27
申请人： Jeremy S. Bridges , William M. Megarity , Luke D. Remis , Gregory D. Sellman
发明人： Jeremy S. Bridges , William M. Megarity , Luke D. Remis , Gregory D. Sellman
IPC分类号： H01R13/62
CPC分类号： G06F1/20 , H01R12/7029 , H01R12/721
摘要： In one embodiment, a memory module connector includes sidewalls extending along a length of the connector body. A longitudinally oriented socket is provided between the sidewalls for receiving a card edge of a memory module. A top of the connector defines a socket opening. A bottom of the connector is for mounting to a system board. A plurality of air deflectors is provided adjacent to the connector body to manipulate airflow to improve cooling. The size, positioning, and spacing of the air deflectors may be selected to optimize cooling.
摘要翻译：在一个实施例中，存储器模块连接器包括沿连接器主体的长度延伸的侧壁。在侧壁之间提供纵向定位的插座，用于接收存储器模块的卡边缘。连接器的顶部定义了插座开口。连接器的底部用于安装到系统板。多个空气导流器邻近连接器主体设置以操纵气流以改善冷却。可以选择空气导流板的尺寸，定位和间距以优化冷却。

7. 发明申请

US20130346835A1 Detecting Data Transmission Errors In An Inter-Integrated Circuit ('I2C') System 有权
标题翻译：检测内部集成电路（“I2C”）系统中的数据传输错误
公开(公告)号：US20130346835A1
公开(公告)日：2013-12-26
申请号：US13530318
申请日：2012-06-22
申请人： Michael DeCesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Michael DeCesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/098 , H04L2001/0094
摘要： Detecting data transmission errors in an I2C system that includes a source device, an destination device, and a signal line coupling the I2C source and destination device, including: receiving, by the I2C destination device from the I2C source device, a data transmission signal, the data transmission signal encoded with a set of bits; detecting, by the I2C destination device, rise time of a preselected bit in the set of bits; if the detected rise time is less than a predefined threshold, determining that the I2C source device injected a parity bit in the signal, and if the detected rise time is not less than the predefined threshold, determining that the I2C source device did not inject a parity bit in the signal; and determining whether the data transmission signal includes an error in dependence upon the parity of the set of bits.
摘要翻译：检测I2C系统中的数据传输错误，该系统包括源设备，目标设备和耦合I2C源设备和目标设备的信号线，包括：由I2C源设备从I2C源设备接收数据传输信号，数据传输信号用一组位编码; 通过I2C目的地设备检测位组中的预选位的上升时间; 如果检测到的上升时间小于预定阈值，则确定I2C源设备在信号中注入了奇偶校验位，并且如果检测到的上升时间不小于预定阈值，则确定I2C源设备未注入信号中的奇偶校验位; 以及确定所述数据传输信号是否包括与所述位组的奇偶校验有关的错误。

8. 发明申请

US20130343197A1 Operating A Demultiplexer On An Inter-Integrated Circuit ('I2C') Bus 有权
标题翻译：在内部集成电路（“I2C”）总线上操作解复用器
公开(公告)号：US20130343197A1
公开(公告)日：2013-12-26
申请号：US13530245
申请日：2012-06-22
申请人： Michael DeCesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Michael DeCesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： H04L12/26
CPC分类号： G06F13/4291
摘要： Operating a demultiplexer on an I2C bus, the demultiplexer including a set of input signal lines from an I2C master and a plurality of sets of output signal lines, the demultiplexer configured to couple the inputs among the output in dependence upon a demultiplexer select signal line that couples the demultiplexer to a rise time detection circuit, where the rise time detection circuit is also coupled to the input signal lines and the rise time detection circuit: monitors a voltage of at least one of the input signal lines, including: receiving, from the I2C master, a signal on one of the lines; and detecting rise time of the signal; and if the rise time of the signal is less than a predefined threshold, configuring the demultiplexer to vary the coupling of the input signal lines from a first set of outputs to a second set.
摘要翻译：在I2C总线上操作解复用器，解复用器包括来自I2C主机和多组输出信号线的一组输入信号线，该多路分配器被配置为根据解复用器选择信号线在输出之间耦合输入将解复用器耦合到上升时间检测电路，其中上升时间检测电路还耦合到输入信号线和上升时间检测电路：监视至少一个输入信号线的电压，包括：从 I2C主机，其中一条信号; 并检测信号的上升时间; 并且如果信号的上升时间小于预定阈值，则配置解复用器以改变输入信号线与第一组输出到第二组的耦合。

9. 发明授权

US08959380B2 Dynamically optimizing bus frequency of an inter-integrated circuit (‘I2C’) bus 有权
标题翻译：动态优化集成电路（“I2C”）总线的总线频率
公开(公告)号：US08959380B2
公开(公告)日：2015-02-17
申请号：US13467332
申请日：2012-05-09
申请人： Michael Decesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Michael Decesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F1/08
CPC分类号： G06F1/324 , G06F9/44 , G06F13/38 , G06F13/4282
摘要： Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.
摘要翻译：优化I2C总线频率，总线包括耦合主节点和从节点的信号线，耦合到上升时间检测电路的信号线监视信号线的电压，电压在逻辑低电平和逻辑高电平之间交替，其中优化频率包括：在信号线上升期间检测第一电压，第一电压大于逻辑低电压; 启动一个计数器，为电路的每个时钟周期增加一次; 检测信号线上的第二电压，第二电压大于第一电压并小于逻辑高电平; 停止柜台根据时钟周期和计数器值计算上升时间; 确定上升时间是否大于最大阈值; 并且如果计算的上升时间大于最大阈值，则增加I2C总线频率。

10. 发明授权

US08954634B2 Operating a demultiplexer on an inter-integrated circuit (‘I2C’) bus 有权
标题翻译：在集成电路（“I2C”）总线上操作多路分解器
公开(公告)号：US08954634B2
公开(公告)日：2015-02-10
申请号：US13530245
申请日：2012-06-22
申请人： Michael DeCesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
发明人： Michael DeCesaris , Steven C. Jacobson , Luke D. Remis , Gregory D. Sellman
IPC分类号： G06F3/00
CPC分类号： G06F13/4291
摘要： Operating a demultiplexer on an I2C bus, the demultiplexer including a set of input signal lines from an I2C master and a plurality of sets of output signal lines, the demultiplexer configured to couple the inputs among the output in dependence upon a demultiplexer select signal line that couples the demultiplexer to a rise time detection circuit, where the rise time detection circuit is also coupled to the input signal lines and the rise time detection circuit: monitors a voltage of at least one of the input signal lines, including: receiving, from the I2C master, a signal on one of the lines; and detecting rise time of the signal; and if the rise time of the signal is less than a predefined threshold, configuring the demultiplexer to vary the coupling of the input signal lines from a first set of outputs to a second set.
摘要翻译：在I2C总线上操作解复用器，解复用器包括来自I2C主机和多组输出信号线的一组输入信号线，该多路分配器被配置为根据解复用器选择信号线在输出之间耦合输入将解复用器耦合到上升时间检测电路，其中上升时间检测电路还耦合到输入信号线和上升时间检测电路：监视至少一个输入信号线的电压，包括：从 I2C主机，其中一条信号; 并检测信号的上升时间; 并且如果信号的上升时间小于预定阈值，则配置解复用器以改变输入信号线与第一组输出到第二组的耦合。

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