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1. 发明授权

US06429482B1 Halo-free non-rectifying contact on chip with halo source/drain diffusion 有权
标题翻译：光环/漏极扩散芯片上的无光非整流接触
公开(公告)号：US06429482B1
公开(公告)日：2002-08-06
申请号：US09589719
申请日：2000-06-08
申请人： James A. Culp , Jawahar P. Nayak , Werner A. Rausch , Melanie J. Sherony , Steven H. Voldman , Noah D. Zamdmer
发明人： James A. Culp , Jawahar P. Nayak , Werner A. Rausch , Melanie J. Sherony , Steven H. Voldman , Noah D. Zamdmer
IPC分类号： H01L2976
CPC分类号： H01L29/4966 , H01L29/1083 , H01L29/7835
摘要： A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.
摘要翻译：半导体芯片包括具有整流接触扩散和非整流接触扩散的半导体衬底。卤素扩散与整流接触扩散相邻，并且没有卤素扩散与非整流接触扩散相邻。整流接触扩散可以是FET的源极/漏极扩散，以提高耐穿透性。非整流接触扩散可以是FET体接触，横向二极管接触或电阻或电容器接触。避免使用非整流触点的光圈可以降低串联电阻并提高器件特性。在具有相邻扩散的光晕的器件的芯片的另一实施例中，没有卤素扩散与横向二极管的整流接触扩散相邻，从而显着地提高了二极管的理想性并增加了击穿电压。

2. 发明授权

US06750109B2 Halo-free non-rectifying contact on chip with halo source/drain diffusion 有权
标题翻译：光环/漏极扩散芯片上的无光非整流接触
公开(公告)号：US06750109B2
公开(公告)日：2004-06-15
申请号：US10064305
申请日：2002-07-01
申请人： James A. Culp , Jawahar P. Nayak , Werner A. Rausch , Melanie J. Sherony , Steven H. Voldman , Noah D. Zamdmer
发明人： James A. Culp , Jawahar P. Nayak , Werner A. Rausch , Melanie J. Sherony , Steven H. Voldman , Noah D. Zamdmer
IPC分类号： H01L21331
CPC分类号： H01L29/4966 , H01L29/1083 , H01L29/7835
摘要： A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.
摘要翻译：半导体芯片包括具有整流接触扩散和非整流接触扩散的半导体衬底。光晕扩散与整流接触扩散相邻，并且没有晕圈扩散与非整流接触扩散相邻。整流接触扩散可以是FET的源极/漏极扩散，以提高耐穿透性。非整流接触扩散可以是FET体接触，横向二极管接触或电阻或电容器接触。避免使用非整流触点的光圈可以降低串联电阻并提高器件特性。在具有相邻扩散的光晕的器件的芯片的另一实施例中，没有卤素扩散与横向二极管的整流接触扩散相邻，从而显着地提高了二极管的理想性并增加了击穿电压。

3. 发明授权

US08423936B2 Semiconductor structure and method of designing semiconductor structure to avoid high voltage initiated latch-up in low voltage sectors 有权
标题翻译：半导体结构和半导体结构设计方法，以避免在低压部分高压启动闭锁
公开(公告)号：US08423936B2
公开(公告)日：2013-04-16
申请号：US13358105
申请日：2012-01-25
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , H01L23/585 , H01L27/0921 , H01L2924/0002 , H01L2924/00
摘要： A method and semiconductor structure to avoid latch-up is disclosed. The method includes identifying at least one high voltage device on a semiconductor chip, identifying a circuit on the semiconductor chip separated from the identified at least one high voltage device by a guard ring, evaluating the circuit for a latch-up condition, and when the latch-up condition occurs, adjusting the contact-circuit spacing in the circuit.
摘要翻译：公开了一种避免闩锁的方法和半导体结构。该方法包括识别半导体芯片上的至少一个高电压器件，识别半导体芯片上的由保护环与所识别的至少一个高电压器件分离的电路，评估该电路的闩锁状态，以及当发生闩锁状态，调整电路中的接触电路间距。

4. 发明授权

US08390074B2 Structure and method for latchup improvement using through wafer via latchup guard ring 有权
标题翻译：用于通过闭锁保护环通过晶片的闩锁改进的结构和方法
公开(公告)号：US08390074B2
公开(公告)日：2013-03-05
申请号：US13150437
申请日：2011-06-01
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L27/0921
摘要： A structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure.
摘要翻译：用于防止闩锁的结构。该结构包括闭锁敏感结构和限制闩锁敏感结构的穿透晶片通孔结构，以防止寄生载流子注入到闩锁敏感结构中。

5. 发明授权

US07977714B2 Wrapped gate junction field effect transistor 有权
标题翻译：封装栅结场效应晶体管
公开(公告)号：US07977714B2
公开(公告)日：2011-07-12
申请号：US11875190
申请日：2007-10-19
申请人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
发明人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/66924
摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
摘要翻译：提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过所述至少一个半导体通道。通过采用多个通道，JFET可以提供高导通电流。

6. 发明授权

US07949983B2 High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature 有权
标题翻译：高容差TCR平衡型高电流电阻，用于射频CMOS和射频SiGe BiCMOS应用以及基于分级的分级参数化电池设计套件，具有可调TCR和ESD电阻镇流功能
公开(公告)号：US07949983B2
公开(公告)日：2011-05-24
申请号：US12234473
申请日：2008-09-19
申请人： Ebenezer E. Eshun , Steven H. Voldman
发明人： Ebenezer E. Eshun , Steven H. Voldman
IPC分类号： G06F17/50
CPC分类号： H01C7/06 , H01L27/0288 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor. A computer aided design tool with graphical and schematic features is provided to enable generation of hierarchical parameterized cells for a resistor element with the ability to provide customization, personalization and tunability of TCR, TCR matching, and high current and ESD robustness.
摘要翻译：因此，电阻器件结构及其制造方法，其中电阻器件结构发明包括多个交替导电膜和绝缘膜层，至少两个导电膜层并联电连接以提供通过电阻器的高电流器件在高频下具有升高的温度和机械稳定性。交替导电膜和绝缘膜层可以是平面或非平面的几何空间取向。交替导电膜和绝缘膜层可以包括横向和垂直部分，其被设计成能够通过物理电阻器内的自镇流效应在结构本身内实现均匀的电流密度流动。提供了具有图形和原理图功能的计算机辅助设计工具，以便能够为电阻元件生成分层参数化单元，具有提供TCR，TCR匹配以及高电流和ESD鲁棒性的定制，个性化和可调性的能力。

7. 发明授权

US07842580B2 Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications 有权
标题翻译： SOI / RF SiGe应用的超高电阻率晶圆掩埋电感的结构和方法
公开(公告)号：US07842580B2
公开(公告)日：2010-11-30
申请号：US12122754
申请日：2008-05-19
申请人： Max G. Levy , Steven H. Voldman
发明人： Max G. Levy , Steven H. Voldman
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L27/0617 , H01L27/08 , H01L28/10
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括高电阻率衬底和直接形成在高电阻率衬底中且在它们之间没有绝缘层的埋地电感器。

8. 发明授权

US07807562B2 Dendrite growth control circuit 失效
标题翻译：树枝生长控制电路
公开(公告)号：US07807562B2
公开(公告)日：2010-10-05
申请号：US12256221
申请日：2008-10-22
申请人： Douglas B. Hershberger , Steven H. Voldman , Michael J. Zierak
发明人： Douglas B. Hershberger , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838
摘要： A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.
摘要翻译：提供了一种电路，其防止由于树突形成电流而在半导体器件处理期间互连上的枝晶形成。电路包括位于至少一个枝晶形成电流路径中的开关。该开关被配置为在处理期间处于打开状态或处于“关闭”状态，并且在处理之后被配置为闭合或处于“接通”状态以允许半导体器件正常工作。开关可以包括nFET或pFET，这取决于其用于控制或防止枝晶形成的环境。当在制造的半导体器件的操作期间提供输入信号时，开关可以被配置为改变为“闭合”状态。

9. 发明授权

US07755161B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US07755161B2
公开(公告)日：2010-07-13
申请号：US12237148
申请日：2008-09-24
申请人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
发明人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L29/00
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/7378
摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
摘要翻译：一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部。该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。

10. 发明申请

US20100025761A1 DESIGN STRUCTURE, STRUCTURE AND METHOD OF LATCH-UP IMMUNITY FOR HIGH AND LOW VOLTAGE INTEGRATED CIRCUITS 有权
标题翻译：高低压集成电路的设计结构，结构和闭锁方法
公开(公告)号：US20100025761A1
公开(公告)日：2010-02-04
申请号：US12183462
申请日：2008-07-31
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L29/94 , H01L29/78 , G06F17/50
CPC分类号： H01L27/092 , H01L21/823892 , H01L27/0921 , H01L29/0638 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/66833 , H01L29/7816 , H01L29/7835 , H01L29/7923
摘要： Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.
摘要翻译：制造结构的设计结构，结构和方法，为混合电压集成电路提供闭锁抑制。该结构包括嵌入在P晶片中并且在逆向N阱下面提供到非隔离CMOS逻辑的扩散N型Tub结构。

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