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1. 发明授权

US07807562B2 Dendrite growth control circuit 失效
标题翻译：树枝生长控制电路
公开(公告)号：US07807562B2
公开(公告)日：2010-10-05
申请号：US12256221
申请日：2008-10-22
申请人： Douglas B. Hershberger , Steven H. Voldman , Michael J. Zierak
发明人： Douglas B. Hershberger , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838
摘要： A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.
摘要翻译：提供了一种电路，其防止由于树突形成电流而在半导体器件处理期间互连上的枝晶形成。电路包括位于至少一个枝晶形成电流路径中的开关。该开关被配置为在处理期间处于打开状态或处于“关闭”状态，并且在处理之后被配置为闭合或处于“接通”状态以允许半导体器件正常工作。开关可以包括nFET或pFET，这取决于其用于控制或防止枝晶形成的环境。当在制造的半导体器件的操作期间提供输入信号时，开关可以被配置为改变为“闭合”状态。

2. 发明授权

US07473643B2 Dendrite growth control circuit 失效
标题翻译：树枝生长控制电路
公开(公告)号：US07473643B2
公开(公告)日：2009-01-06
申请号：US11461623
申请日：2006-08-01
申请人： Douglas B. Hershberger , Steven H. Voldman , Michael J. Zierak
发明人： Douglas B. Hershberger , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L21/44
CPC分类号： H01L21/76838
摘要： A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.
摘要翻译：提供一种电路，其防止由于树突形成电流而在半导体器件处理期间互连上的枝晶形成。电路包括位于至少一个枝晶形成电流路径中的开关。该开关被配置为在处理期间处于打开状态或处于“关闭”状态，并且在处理之后被配置为闭合或处于“接通”状态以允许半导体器件正常工作。开关可以包括nFET或pFET，这取决于其用于控制或防止枝晶形成的环境。当在制造的半导体器件的操作期间提供输入信号时，开关可以被配置为改变为“闭合”状态。

3. 发明授权

US07109584B2 Dendrite growth control circuit 有权
公开(公告)号：US07109584B2
公开(公告)日：2006-09-19
申请号：US10904680
申请日：2004-11-23
申请人： Douglas B. Hershberger , Steven H. Voldman , Michael J. Zierak
发明人： Douglas B. Hershberger , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76838
摘要： A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.

4. 发明申请

US20090035933A1 DENDRITE GROWTH CONTROL CIRCUIT 失效
标题翻译：浸润生长控制电路
公开(公告)号：US20090035933A1
公开(公告)日：2009-02-05
申请号：US12256221
申请日：2008-10-22
申请人： Douglas B. Hershberger , Steven H. Voldman , Michael J. Zierak
发明人： Douglas B. Hershberger , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838
摘要： A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.
摘要翻译：提供一种电路，其防止由于树突形成电流而在半导体器件处理期间互连上的枝晶形成。电路包括位于至少一个枝晶形成电流路径中的开关。该开关被配置为在处理期间处于打开状态或处于“关闭”状态，并且在处理之后被配置为闭合或处于“接通”状态以允许半导体器件正常工作。开关可以包括nFET或pFET，这取决于其用于控制或防止枝晶形成的环境。当在制造的半导体器件的操作期间提供输入信号时，开关可以被配置为改变为“闭合”状态。

5. 发明授权

US06396107B1 Trench-defined silicon germanium ESD diode network 有权
标题翻译：沟槽定义的硅锗ESD二极管网络
公开(公告)号：US06396107B1
公开(公告)日：2002-05-28
申请号：US09716749
申请日：2000-11-20
申请人： Ciaran J. Brennan , Douglas B. Hershberger , Mankoo Lee , Nicholas T. Schmidt , Steven H. Voldman
发明人： Ciaran J. Brennan , Douglas B. Hershberger , Mankoo Lee , Nicholas T. Schmidt , Steven H. Voldman
IPC分类号： H01L2362
CPC分类号： H01L27/0259 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A silicon-germanium ESD element comprises a substrate of a first dopant type coupled to a first voltage terminal and a first diode-configured element. The first diode-configured element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. Preferably, the SiGe base layer ion the collector region is an epitaxial SiGe layer and the second dopant type of the emitter is diffused in to the SiGe base layer. The ESD element of the present invention may further include a second diode-configured element of the same structure as the first diode-configured element, with an isolation region in the substrate separating the first and second diode-configured elements. The first and second diode-configured elements form a diode network. In each of the embodiments, the isolation regions may be disposed adjacent the collector regions of the diode elements and below a portion of the SiGe base layer of the diode elements. The SiGe base layer in the diode elements preferably comprises an active, single crystal layer in a portion directly over the collector region and a polycrystalline layer in portions directly over the isolation regions. The isolation regions may be shallow or deep trench isolations.
摘要翻译：硅锗ESD元件包括耦合到第一电压端子和第一二极管配置元件的第一掺杂剂类型的衬底。第一二极管配置元件在衬底中具有第二掺杂剂类型的集电极区域，在集电极区域上具有第一掺杂剂类型的SiGe基极层，SiGe基极层包括基极接触区域，第二掺杂剂的发射极掺杂剂类型在SiGe基层上。优选地，SiGe基极层离子集电极区域是外延SiGe层，并且第二掺杂剂类型的发射极扩散到SiGe基极层中。本发明的ESD元件还可以包括与第一二极管配置元件相同结构的第二二极管配置元件，衬底中的隔离区域分隔第一和第二二极管配置元件。第一和第二二极管配置元件形成二极管网络。在每个实施例中，隔离区可以邻近二极管元件的集电极区域并且位于二极管元件的SiGe基极层的一部分附近。二极管元件中的SiGe基极层优选地包括直接在集电极区域上的部分中的有源单晶层和直接在隔离区上的部分的多晶层。隔离区可以是浅沟或深沟隔离。

6. 发明授权

US07977714B2 Wrapped gate junction field effect transistor 有权
标题翻译：封装栅结场效应晶体管
公开(公告)号：US07977714B2
公开(公告)日：2011-07-12
申请号：US11875190
申请日：2007-10-19
申请人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
发明人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/66924
摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
摘要翻译：提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过所述至少一个半导体通道。通过采用多个通道，JFET可以提供高导通电流。

7. 发明申请

US20090101941A1 WRAPPED GATE JUNCTION FIELD EFFECT TRANSISTOR 有权
标题翻译：封装栅极连接场效应晶体管
公开(公告)号：US20090101941A1
公开(公告)日：2009-04-23
申请号：US11875190
申请日：2007-10-19
申请人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
发明人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/66924
摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
摘要翻译：提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过所述至少一个半导体通道。通过采用多个通道，JFET可以提供高导通电流。

8. 发明授权

US07348251B2 Modulated trigger device 失效
标题翻译：调制触发器
公开(公告)号：US07348251B2
公开(公告)日：2008-03-25
申请号：US11201023
申请日：2005-08-10
申请人： Steven H. Voldman , Michael J. Zierak
发明人： Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/66
CPC分类号： H01L27/0277 , H01L29/1087 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure, a trigger device and a method of electrostatic discharge protection, the integrated circuit structure including: a substrate having a top surface defining a horizontal direction, the substrate of a first dopant type; a first horizontal layer in the substrate, the first layer of a second dopant type; and a second horizontal layer of the first dopant type, the second layer on top of the first layer and between the top surface of the substrate and the first layer, the second layer electrically modulated by the first layer.
摘要翻译：集成电路结构，触发装置和静电放电保护方法，所述集成电路结构包括：具有限定水平方向的顶表面的衬底，所述第一掺杂剂类型的衬底; 衬底中的第一水平层，第二掺杂剂型的第一层; 以及第一掺杂剂类型的第二水平层，第二层在第一层的顶部和衬底的顶表面与第一层之间，第二层由第一层电调制。

9. 发明授权

US07886240B2 Modifying layout of IC based on function of interconnect and related circuit and design structure 有权
标题翻译：基于互连功能和相关电路以及设计结构修改IC布局
公开(公告)号：US07886240B2
公开(公告)日：2011-02-08
申请号：US12021333
申请日：2008-01-29
申请人： James W. Adkisson , Natalie B. Feilchenfeld , Jeffrey P. Gambino , Howard S. Landis , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
发明人： James W. Adkisson , Natalie B. Feilchenfeld , Jeffrey P. Gambino , Howard S. Landis , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
IPC分类号： G06F17/50 , G06F7/38 , H01L25/00 , H03K19/00
CPC分类号： G06F17/5081
摘要： Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect.
摘要翻译：公开了基于互连功能的集成电路（IC）的布局以及相关的电路和设计结构。在一个实施例中，一种方法包括根据体现在计算机可读介质中的布局的数据来识别布局中的互连的功能; 并修改布局以形成适应互连功能的另一布局。根据一个实施例，体现在设计过程中使用的机器可读介质中的设计结构可以包括电路，该电路包括定位在电介质层中的高电压互连，所述高压互连被定位成使得没有填充物高于或低于高电压互连。

10. 发明申请

US20090261426A1 LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE 有权
标题翻译：具有排水区域的侧向扩散场效应晶体管与电极电极对齐
公开(公告)号：US20090261426A1
公开(公告)日：2009-10-22
申请号：US12104643
申请日：2008-04-17
申请人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
发明人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/1045 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.
摘要翻译：形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。因此，漏极区域与栅电极的边缘自对准。一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。在形成漏极区域之后，一次性结构被去除。漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。

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