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1. 发明授权

US08264022B2 Semiconductor device including contact plug and associated methods 有权
标题翻译：包括接触插头和相关方法的半导体器件
公开(公告)号：US08264022B2
公开(公告)日：2012-09-11
申请号：US12588790
申请日：2009-10-28
申请人： Jae-man Yoon , Gyo-young Jin , Hyeong-sun Hong , Makoto Yoshida , Bong-soo Kim
发明人： Jae-man Yoon , Gyo-young Jin , Hyeong-sun Hong , Makoto Yoshida , Bong-soo Kim
IPC分类号： H01L21/70 , H01L21/8246 , H01L27/22
CPC分类号： H01L21/76834 , H01L21/76816 , H01L23/485 , H01L27/10855 , H01L27/10888 , H01L27/11 , H01L27/11517 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.
摘要翻译：一种半导体器件及相关方法，所述半导体器件包括包括第一区域和第二区域的半导体层，设置在半导体层上并与第一区域电连接的第一接触插塞，设置在半导体层上的第二接触插塞和电连接到第二区域，导电层电连接到第一接触插塞，导电层具有侧表面和底表面，以及绝缘层，设置在导电层和第二接触插塞之间，以使导电层，所述绝缘层面向所述导电层的侧表面和所述底表面的一部分。

2. 发明申请

US20100207241A1 Semiconductor device including contact plug and associated methods 有权
标题翻译：包括接触插头和相关方法的半导体器件
公开(公告)号：US20100207241A1
公开(公告)日：2010-08-19
申请号：US12588790
申请日：2009-10-28
申请人： Jae-man Yoon , Gyo-young Jin , Hyeong-sun Hong , Makoto Yoshida , Bong-soo Kim
发明人： Jae-man Yoon , Gyo-young Jin , Hyeong-sun Hong , Makoto Yoshida , Bong-soo Kim
IPC分类号： H01L23/485 , H01L29/92
CPC分类号： H01L21/76834 , H01L21/76816 , H01L23/485 , H01L27/10855 , H01L27/10888 , H01L27/11 , H01L27/11517 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and associated methods, the semiconductor device including a semiconductor layer including a first region and a second region, a first contact plug disposed on the semiconductor layer and electrically connected to the first region, a second contact plug disposed on the semiconductor layer and electrically connected to the second region, a conductive layer electrically connected to the first contact plug, the conductive layer having a side surface and a bottom surface, and an insulating layer disposed between the conductive layer and the second contact plug so as to insulate the conductive layer from the second contact plug, the insulating layer facing the side surface and a portion of the bottom surface of the conductive layer.
摘要翻译：一种半导体器件和相关方法，所述半导体器件包括包括第一区域和第二区域的半导体层，设置在半导体层上并电连接到第一区域的第一接触插塞，设置在半导体层上的第二接触插塞和电连接到第二区域，导电层电连接到第一接触插塞，导电层具有侧表面和底表面，以及绝缘层，设置在导电层和第二接触插塞之间，以使导电层，所述绝缘层面向所述导电层的侧表面和所述底表面的一部分。

3. 发明授权

US07265011B2 Method of manufacturing a transistor 失效
标题翻译：制造晶体管的方法
公开(公告)号：US07265011B2
公开(公告)日：2007-09-04
申请号：US10898484
申请日：2004-07-22
申请人： Jae-Man Yoon , Dong-gun Park , Makoto Yoshida , Gyo-Young Jin , Jeong-dong Choe , Sang-Yeon Han
发明人： Jae-Man Yoon , Dong-gun Park , Makoto Yoshida , Gyo-Young Jin , Jeong-dong Choe , Sang-Yeon Han
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/823425 , H01L21/823814 , H01L21/823828 , H01L21/82385 , H01L29/66537
摘要： A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.
摘要翻译：根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区，并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成栅极区域中的第三杂质区域。该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。

4. 发明申请

US20050048729A1 Method of manufacturing a transistor 失效
标题翻译：制造晶体管的方法
公开(公告)号：US20050048729A1
公开(公告)日：2005-03-03
申请号：US10898484
申请日：2004-07-22
申请人： Jae-Man Yoon , Dong-gun Park , Makoto Yoshida , Gyo-Young Jin , Jeong-dong Choe , Sang-Yeon Han
发明人： Jae-Man Yoon , Dong-gun Park , Makoto Yoshida , Gyo-Young Jin , Jeong-dong Choe , Sang-Yeon Han
IPC分类号： H01L21/334 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66545 , H01L21/823425 , H01L21/823814 , H01L21/823828 , H01L21/82385 , H01L29/66537
摘要： A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.
摘要翻译：根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区，并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成栅极区域中的第三杂质区域。该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。

5. 发明申请

US20110095350A1 VERTICAL TYPE INTEGRATED CIRCUIT DEVICES, MEMORY DEVICES, AND METHODS OF FABRICATING THE SAME 有权
标题翻译：垂直型集成电路装置，存储装置及其制造方法
公开(公告)号：US20110095350A1
公开(公告)日：2011-04-28
申请号：US12891910
申请日：2010-09-28
申请人： Jae-man Yoon , Hyeong-sun Hong , Kwang-youl Chun , Makoto Yoshida , Deok-sung Hwang , Chul Lee
发明人： Jae-man Yoon , Hyeong-sun Hong , Kwang-youl Chun , Makoto Yoshida , Deok-sung Hwang , Chul Lee
IPC分类号： H01L27/108 , H01L29/78
CPC分类号： H01L27/10897 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L29/0657 , H01L29/42356 , H01L29/66666 , H01L29/7827
摘要： A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.
摘要翻译：垂直型集成电路装置包括基板和从基板垂直突出的支柱。支柱包括其中较低的杂质区域和上部杂质区域以及它们之间的垂直沟道区域。包括其中较低杂质区域的柱的一部分包括从其横向延伸的台面。该器件还包括在柱的第一侧壁上延伸并与下部杂质区电接触的第一导电线，以及在邻近垂直沟道区的柱的第二侧壁上延伸的第二导电线。第二导电线在垂直于第一导电线的方向上延伸并且与台面间隔开。还讨论了相关装置和制造方法。

6. 发明授权

US08791526B2 Vertical type integrated circuit devices and memory devices including conductive lines supported by Mesa structures and methods of fabricating the same 有权
标题翻译：包括由Mesa结构支撑的导电线的垂直型集成电路器件和存储器件及其制造方法
公开(公告)号：US08791526B2
公开(公告)日：2014-07-29
申请号：US12891910
申请日：2010-09-28
申请人： Jae-man Yoon , Hyeong-sun Hong , Kwang-youl Chun , Makoto Yoshida , Deok-sung Hwang , Chul Lee
发明人： Jae-man Yoon , Hyeong-sun Hong , Kwang-youl Chun , Makoto Yoshida , Deok-sung Hwang , Chul Lee
IPC分类号： H01L29/66
CPC分类号： H01L27/10897 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L29/0657 , H01L29/42356 , H01L29/66666 , H01L29/7827
摘要： A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.
摘要翻译：垂直型集成电路装置包括基板和从基板垂直突出的支柱。支柱包括其中较低的杂质区域和上部杂质区域以及它们之间的垂直沟道区域。包括其中较低杂质区域的柱的一部分包括从其横向延伸的台面。该器件还包括在柱的第一侧壁上延伸并与下部杂质区电接触的第一导电线，以及在邻近垂直沟道区的柱的第二侧壁上延伸的第二导电线。第二导电线在垂直于第一导电线的方向上延伸并且与台面间隔开。还讨论了相关装置和制造方法。

7. 发明授权

US07977204B2 Method of forming a fine pattern of a semiconductor device using a double patterning technique 有权
标题翻译：使用双重图案形成技术形成半导体器件的精细图案的方法
公开(公告)号：US07977204B2
公开(公告)日：2011-07-12
申请号：US12485970
申请日：2009-06-17
申请人： Yong-il Kim , Hyeong-sun Hong , Makoto Yoshida , Bong-soo Kim
发明人： Yong-il Kim , Hyeong-sun Hong , Makoto Yoshida , Bong-soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A method of forming a fine pattern of a semiconductor device uses a double patterning technique. A first mask pattern is formed on a first hard mask layer disposed on a substrate. A conformal buffer layer is formed over the first mask pattern. A second mask pattern is formed such that segments of the buffer layer are interposed between the first and second mask patterns, and each topographical feature of the second mask pattern is disposed between two adjacent ones of each respective pair of topographical features of the first mask pattern. A first hard mask pattern is formed by etching the first hard mask layer using the first mask pattern, the second mask pattern, and/or the buffer layer as an etch mask. A trench is formed by etching the substrate using the first hard mask pattern as an etch mask. An isolation layer, of a material that is different from that of first hard mask pattern, is formed in the trench.
摘要翻译：形成半导体器件的精细图案的方法使用双重图案化技术。在设置在基板上的第一硬掩模层上形成第一掩模图案。在第一掩模图案之上形成共形缓冲层。形成第二掩模图案，使得缓冲层的段插入在第一和第二掩模图案之间，并且第二掩模图案的每个形貌特征被布置在第一掩模图案的每个相应的一对地形特征中的两个相邻的特征之间。通过使用第一掩模图案，第二掩模图案和/或缓冲层作为蚀刻掩模蚀刻第一硬掩模层来形成第一硬掩模图案。通过使用第一硬掩模图案作为蚀刻掩模蚀刻衬底来形成沟槽。在沟槽中形成与第一硬掩模图案不同的材料的隔离层。

8. 发明申请

US20090181510A1 Method of manufacturing semiconductor device including isolation process 有权
标题翻译：制造半导体器件的方法包括隔离工艺
公开(公告)号：US20090181510A1
公开(公告)日：2009-07-16
申请号：US12213174
申请日：2008-06-16
申请人： Yong-il Kim , Hyeong-sun Hong , Makoto Yoshida
发明人： Yong-il Kim , Hyeong-sun Hong , Makoto Yoshida
IPC分类号： H01L21/8234
CPC分类号： H01L27/105 , H01L21/823481 , H01L27/0207
摘要： Provided may be a method of manufacturing a semiconductor device. The method may include forming a plurality of isolation patterns including conductive patterns on a semiconductor substrate and forming gaps between the isolation patterns, forming active patterns filling the gaps on the semiconductor substrate, forming a gate insulation layer on the isolation patterns and the active patterns, and forming gate patterns on the gate insulation layer.
摘要翻译：可以提供制造半导体器件的方法。该方法可以包括在半导体衬底上形成包括导电图案的多个隔离图案，并且在隔离图案之间形成间隙，形成填充半导体衬底上的间隙的有源图案，在隔离图案上形成栅极绝缘层和活性图案，以及在栅极绝缘层上形成栅极图案。

9. 发明申请

US20100193880A1 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20100193880A1
公开(公告)日：2010-08-05
申请号：US12662150
申请日：2010-04-01
申请人： Makoto Yoshida , Hyeong-Sun Hong , Kye-Hee Yeom , Dae-Ik Kim , Yong-Il Kim
发明人： Makoto Yoshida , Hyeong-Sun Hong , Kye-Hee Yeom , Dae-Ik Kim , Yong-Il Kim
IPC分类号： H01L23/52 , H01L27/088
CPC分类号： H01L27/10894 , H01L21/82345 , H01L21/823456 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L29/4236 , H01L29/66621
摘要： A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.
摘要翻译：半导体器件及其形成方法包括在半导体衬底上形成单元位线图案和外围栅极图案。单元位线图案可以形成在与半导体基板的单元有源区域相邻的非活性区域上。外围栅极图案可以设置在半导体衬底的外围有源区上。细胞接触插塞可以形成在细胞位线图案和细胞活性区域之间。周边接触插塞可以形成在外围栅极图案侧的外围有源区域上。可以形成绝缘层，以将电池位线图形，外围栅极图案，电池和外围接触插头的顶表面暴露在基本上相同的水平。

10. 发明授权

US08120123B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08120123B2
公开(公告)日：2012-02-21
申请号：US12662150
申请日：2010-04-01
申请人： Makoto Yoshida , Hyeong-Sun Hong , Kye-Hee Yeom , Dae-Ik Kim , Yong-Il Kim
发明人： Makoto Yoshida , Hyeong-Sun Hong , Kye-Hee Yeom , Dae-Ik Kim , Yong-Il Kim
IPC分类号： H01L23/52 , H01L27/088
CPC分类号： H01L27/10894 , H01L21/82345 , H01L21/823456 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L29/4236 , H01L29/66621
摘要： A semiconductor device, and a method of forming the same, includes forming a cell bit line pattern and a peripheral gate pattern on a semiconductor substrate. The cell bit line pattern may be formed on an inactive region adjacent to a cell active region of the semiconductor substrate. The peripheral gate pattern may be disposed on a peripheral active region of the semiconductor substrate. A cell contact plug may be formed between the cell bit line pattern and the cell active region. A peripheral contact plug may be formed on the peripheral active region on a side of the peripheral gate pattern. An insulating layer may be formed to expose top surfaces of the cell bit line pattern, the peripheral gate pattern, and the cell and peripheral contact plugs at substantially the same level.
摘要翻译：半导体器件及其形成方法包括在半导体衬底上形成单元位线图案和外围栅极图案。单元位线图案可以形成在与半导体基板的单元有源区域相邻的非活性区域上。外围栅极图案可以设置在半导体衬底的外围有源区上。细胞接触插塞可以形成在细胞位线图案和细胞活性区域之间。周边接触插塞可以形成在外围栅极图案侧的外围有源区域上。可以形成绝缘层，以将电池位线图形，外围栅极图案，电池和外围接触插头的顶表面暴露在基本上相同的水平。

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