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1. 发明申请

US20050286285A1 Semiconductor memory device and method of arranging signal and power lines thereof 有权
标题翻译：半导体存储器件及其信号和电源线的布置方法
公开(公告)号：US20050286285A1
公开(公告)日：2005-12-29
申请号：US11134855
申请日：2005-05-19
申请人： Jae-Young Lee , Joon-Hyuk Kwon , Chi-Wook Kim , Sung-Hoon Kim , Youn-Sik Park
发明人： Jae-Young Lee , Joon-Hyuk Kwon , Chi-Wook Kim , Sung-Hoon Kim , Youn-Sik Park
IPC分类号： G11C5/06 , G11C5/14 , G11C11/4074
CPC分类号： G11C5/14 , G11C5/063 , G11C11/4074
摘要： Method and apparatus for use, e.g., with Synchronous Dynamic Random Access Memory (SDRAM) circuits are disclosed. In one described embodiment, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM. Relatively wide power conductors are routed on a third metal layer, allowing power conductors to be reduced in size, or in some cases eliminated, on first and second metal layers. The relatively wide power conductors thus can provide a more stable power supply to the memory array, and also free some space on first and/or second metal for routing of additional and/or more widely spaced signal conductors. Other embodiments are described and claimed.
摘要翻译：公开了使用例如同步动态随机存取存储器（SDRAM）电路的方法和装置。在一个所描述的实施例中，沉积三层金属层并依次叠置在SDRAM的存储器阵列部分上。相对宽的电力导体在第三金属层上布线，允许在第一和第二金属层上的电力导体的尺寸减小或在某些情况下被消除。因此，相对宽的电力导体可以向存储器阵列提供更稳定的电源，并且还释放第一和/或第二金属上的一些空间，用于路由额外的和/或更广泛间隔的信号导体。描述和要求保护其他实施例。

2. 发明授权

US07161823B2 Semiconductor memory device and method of arranging signal and power lines thereof 有权
标题翻译：半导体存储器件及其信号和电源线的布置方法
公开(公告)号：US07161823B2
公开(公告)日：2007-01-09
申请号：US11134855
申请日：2005-05-19
申请人： Jae-Young Lee , Joon-Hyuk Kwon , Chi-Wook Kim , Sung-Hoon Kim , Youn-Sik Park
发明人： Jae-Young Lee , Joon-Hyuk Kwon , Chi-Wook Kim , Sung-Hoon Kim , Youn-Sik Park
IPC分类号： G11C5/06
CPC分类号： G11C5/14 , G11C5/063 , G11C11/4074
摘要： Method and apparatus for use, e.g., with Synchronous Dynamic Random Access Memory (SDRAM) circuits are disclosed. In one described embodiment, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM. Relatively wide power conductors are routed on a third metal layer, allowing power conductors to be reduced in size, or in some cases eliminated, on first and second metal layers. The relatively wide power conductors thus can provide a more stable power supply to the memory array, and also free some space on first and/or second metal for routing of additional and/or more widely spaced signal conductors. Other embodiments are described and claimed.
摘要翻译：公开了使用例如同步动态随机存取存储器（SDRAM）电路的方法和装置。在一个所描述的实施例中，沉积三层金属层并依次叠置在SDRAM的存储器阵列部分上。相对宽的电力导体在第三金属层上布线，允许在第一和第二金属层上的电力导体的尺寸减小或在某些情况下被消除。因此，相对宽的电力导体可以向存储器阵列提供更稳定的电源，并且还释放第一和/或第二金属上的一些空间，用于路由额外的和/或更广泛间隔的信号导体。描述和要求保护其他实施例。

3. 发明授权

US07391636B2 Semiconductor memory device and arrangement method thereof 失效
标题翻译：半导体存储器件及其布置方法
公开(公告)号：US07391636B2
公开(公告)日：2008-06-24
申请号：US11863151
申请日：2007-09-27
申请人： Chul-Woo Park , Sung-Hoon Kim , Hyuk-Joon Kwon , Jung-Bae Lee , Youn-Sik Park
发明人： Chul-Woo Park , Sung-Hoon Kim , Hyuk-Joon Kwon , Jung-Bae Lee , Youn-Sik Park
IPC分类号： G11C5/06
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C7/18 , H01L23/5226 , H01L27/0203 , H01L27/105 , H01L27/1052 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device and an arrangement method thereof are included. The semiconductor memory device includes column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.
摘要翻译：包括半导体存储器件及其布置方法。半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线布置在不同层上的第二本地数据IO信号线。

4. 发明申请

US20060055045A1 Semiconductor memory device and arrangement method thereof 失效
标题翻译：半导体存储器件及其布置方法
公开(公告)号：US20060055045A1
公开(公告)日：2006-03-16
申请号：US11225221
申请日：2005-09-12
申请人： Chul-Woo Park , Sung-Hoon Kim , Hyuk-Joon Kwon , Jung-Bae Lee , Youn-Sik Park
发明人： Chul-Woo Park , Sung-Hoon Kim , Hyuk-Joon Kwon , Jung-Bae Lee , Youn-Sik Park
IPC分类号： H01L29/40
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C7/18 , H01L23/5226 , H01L27/0203 , H01L27/105 , H01L27/1052 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.
摘要翻译：公开了一种半导体存储器件及其布置方法。半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线布置在不同层上的第二本地数据IO信号线。

5. 发明授权

US07679985B2 Semiconductor memory device and arrangement method thereof 失效
标题翻译：半导体存储器件及其布置方法
公开(公告)号：US07679985B2
公开(公告)日：2010-03-16
申请号：US11863141
申请日：2007-09-27
申请人： Chul-Woo Park , Sung-Hoon Kim , Hyuk-Joon Kwon , Jung-Bae Lee , Youn-Sik Park
发明人： Chul-Woo Park , Sung-Hoon Kim , Hyuk-Joon Kwon , Jung-Bae Lee , Youn-Sik Park
IPC分类号： G11C8/00
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C7/18 , H01L23/5226 , H01L27/0203 , H01L27/105 , H01L27/1052 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.
摘要翻译：公开了一种半导体存储器件及其布置方法。半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线布置在不同层上的第二本地数据IO信号线。

6. 发明授权

US07295454B2 Semiconductor memory device and arrangement method thereof 失效
标题翻译：半导体存储器件及其布置方法
公开(公告)号：US07295454B2
公开(公告)日：2007-11-13
申请号：US11225221
申请日：2005-09-12
申请人： Chul-Woo Park , Sung-Hoon Kim , Hyuk-Joon Kwon , Jung-Bae Lee , Youn-Sik Park
发明人： Chul-Woo Park , Sung-Hoon Kim , Hyuk-Joon Kwon , Jung-Bae Lee , Youn-Sik Park
IPC分类号： G11C5/06
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C7/18 , H01L23/5226 , H01L27/0203 , H01L27/105 , H01L27/1052 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.
摘要翻译：公开了一种半导体存储器件及其布置方法。半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线布置在不同层上的第二本地数据IO信号线。

7. 发明授权

US07133324B2 Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same 有权
标题翻译：具有双数据速率1（DDR1）和DDR2操作模式的同步动态随机存取存储器件及其操作方法
公开(公告)号：US07133324B2
公开(公告)日：2006-11-07
申请号：US11021889
申请日：2004-12-23
申请人： Youn-Sik Park , Sang-Joon Hwang
发明人： Youn-Sik Park , Sang-Joon Hwang
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1012 , G11C7/1045 , G11C7/1066 , G11C7/1072 , G11C11/4076
摘要： A dual data rate dynamic random access memory (DDR DRAM) device may operate in dual DDR modes via a mode selection circuit configured to enable a Dual Data Rate (DDR) 1 mode of operation for the DDR DRAM or a DDR2 mode of operation for the DDR DRAM.
摘要翻译：双数据速率动态随机存取存储器（DDR DRAM）设备可以通过模式选择电路在双DDR模式下工作，该模式选择电路被配置为使能DDR DRAM的双数据速率（DDR）1操作模式或DDR2操作模式 DDR DRAM。

8. 发明授权

US07944130B2 Multi-cantilever MEMS sensor, manufacturing method thereof, sound source localization apparatus using the multi-cantilever MEMS sensor, sound source localization method using the sound source localization apparatus 有权
标题翻译：多悬臂MEMS传感器及其制造方法，使用多悬臂MEMS传感器的声源定位装置，使用声源定位装置的声源定位方法
公开(公告)号：US07944130B2
公开(公告)日：2011-05-17
申请号：US12189544
申请日：2008-08-11
申请人： Youngjin Park , Youn-Sik Park , Jin-Young Kim , Hyun Jo , Seung Seob Lee , Yong Chul Kim
发明人： Youngjin Park , Youn-Sik Park , Jin-Young Kim , Hyun Jo , Seung Seob Lee , Yong Chul Kim
IPC分类号： H01L41/04
CPC分类号： B81B7/04 , B81B2201/0257 , G01S3/8083 , G01S3/82 , H04R21/00 , H04R23/006 , H04R31/00 , H04R2201/003
摘要： Disclosed herein is a multi-cantilever MEMS sensor functioning as a mechanical sensor having a plurality of cantilevers, replacing a conventional DSP based sound source localization algorithm and reducing production cost when the MEMES sensor applied to mass-produced robots, a manufacturing method thereof, a sound source localization apparatus using the multi-cantilever MEMS sensor and a sound source localization method using the sound source localization apparatus. The multi-cantilever MEMS sensor comprises a plurality of cantilevers 100 each of which includes a piezoresistor 20 and a sensing part 30 for sensing a predetermined signal generated according to the piezoresistor 20; and a terminal T for detecting the signal generated according to the piezoresistor 20, wherein one end of each cantilever is a free end and the other end thereof is a fixed end of each cantilever, the piezoresistor 20 and the sensing part 30 are formed at the fixed end, and the free ends of the plurality of cantilevers 100 have different lengths. A method of manufacturing the multi-cantilever MEMS sensor is provided. Furthermore, a method of using the multi-cantilever MEMS sensor and a sound source localization apparatus are provided.
摘要翻译：本文公开了一种多悬臂MEMS传感器，其作为具有多个悬臂的机械传感器，替代了传统的基于DSP的声源定位算法，并且当MEMES传感器应用于大规模生产的机器人时降低了生产成本，其制造方法，使用多悬臂MEMS传感器的声源定位装置和使用声源定位装置的声源定位方法。多悬臂MEMS传感器包括多个悬臂100，每个悬臂100包括压敏电阻20和感测部分30，用于感测根据压电电阻器20产生的预定信号; 以及用于检测根据压敏电阻器20产生的信号的端子T，其中每个悬臂的一端是自由端，另一端是每个悬臂的固定端，压电电阻20和感测部30形成在固定端，并且多个悬臂100的自由端具有不同的长度。提供了制造多悬臂MEMS传感器的方法。此外，提供了使用多悬臂MEMS传感器和声源定位装置的方法。

9. 发明申请

US20080094932A1 Semiconductor memory device and methods thereof 有权
标题翻译：半导体存储器件及其方法
公开(公告)号：US20080094932A1
公开(公告)日：2008-04-24
申请号：US11702569
申请日：2007-02-06
申请人： Min-Sang Park , Jeong-Don Lim , Youn-Sik Park
发明人： Min-Sang Park , Jeong-Don Lim , Youn-Sik Park
IPC分类号： G11C8/18 , G11C29/00 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1039 , G11C7/1072 , G11C8/18 , G11C29/20 , G11C2029/3602 , G11C2207/2245
摘要： A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles. An example method may for achieving an single pumped address (SPA) mode in a semiconductor memory device configured for a double pumped address (DPA) mode may include receiving a first external address, generating a first internal address corresponding to the received first external address, receiving a second external address, generating a second internal address corresponding to the received second external address and delaying the generation of the first internal address to reduce a clock cycle interval between the generated first and second internal addresses.
摘要翻译：提供半导体存储器件及其方法。示例性半导体存储器件可以包括在正常操作期间根据第一寻址协议操作并且在测试操作期间根据第二寻址协议操作的内部地址产生电路，与第一数量的时钟周期相关联的第一寻址协议用于传送存储器地址和与第二数量的时钟周期相关联的用于传送存储器地址的第二寻址协议，第一数量的时钟周期大于第二数量的时钟周期。在针对双抽取地址（DPA）模式配置的半导体存储器件中实现单个泵浦地址（SPA）模式的示例性方法可包括：接收第一外部地址，产生对应于所接收的第一外部地址的第一内部地址，接收第二外部地址，产生对应于所接收的第二外部地址的第二内部地址，并延迟第一内部地址的产生，以减小所生成的第一和第二内部地址之间的时钟周期间隔。

10. 发明授权

US07268579B2 Semiconductor integrated circuit having on-chip termination 有权
标题翻译：具有片上终端的半导体集成电路
公开(公告)号：US07268579B2
公开(公告)日：2007-09-11
申请号：US11030302
申请日：2005-01-07
申请人： Youn-Sik Park
发明人： Youn-Sik Park
IPC分类号： H03K17/16
CPC分类号： H04L25/028 , H04L25/0278
摘要： A semiconductor integrated circuit includes at least one pad coupled to at least one bus line, the at least one pad having a first side, a second side, a third side, and a fourth side; a transmitter for transmitting a signal from an internal circuit externally via the at least one pad; and a termination circuit for terminating the at least one bus line. Either one of the transmitter and the termination circuit is disposed to face the first and second sides of the at least one pad and the other of the transmitter and the termination circuit is disposed to either one of the third and fourth sides of the at least one pad.
摘要翻译：半导体集成电路包括耦合到至少一个总线的至少一个焊盘，所述至少一个焊盘具有第一侧，第二侧，第三侧和第四侧; 发送器，用于经由所述至少一个衬垫从外部发送来自内部电路的信号; 以及用于终止所述至少一条总线线路的终端电路。发射机和终端电路中的任何一个设置成面对至少一个焊盘的第一和第二侧，并且发射器和终端电路中的另一个设置在至少一个焊盘的第三和第四侧中的任一个上垫。

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