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    • 1. 发明申请
    • Vertical pillar transistor
    • 立柱晶体管
    • US20090242975A1
    • 2009-10-01
    • US12382898
    • 2009-03-26
    • Hui-Jung KimYong-Chul OhJae-Man YoonHyun-Woo ChungHyun-Gi KimKang-Uk Kim
    • Hui-Jung KimYong-Chul OhJae-Man YoonHyun-Woo ChungHyun-Gi KimKang-Uk Kim
    • H01L29/78H01L21/336
    • H01L27/10882H01L21/76232H01L21/823481H01L21/823487H01L27/10876H01L29/66666H01L29/7827
    • A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of lower pillars extends along a second direction and may be separated from each other along a first direction substantially perpendicular to the second direction. The plurality of upper pillars may be formed on the plurality of lower pillars. The plurality of upper pillars has a width substantially smaller than that of the plurality of lower pillars. The first insulation part has a substantially uniform thickness on a sidewall of each of the plurality of lower pillars. The second insulation part may be formed on the first insulation part to fill a gap between the adjacent upper pillars. The word line may be formed on the second insulation part and may extend between facing sidewalls of the adjacent pair of upper pillars along the first direction.
    • 垂直柱状晶体管可以包括多个下部支柱,多个上部支柱,第一绝缘部分,第二绝缘部分和字线。 多个下支柱基本上垂直于基板突出并且由多个沟槽限定。 多个下柱沿着第二方向延伸并且可以沿着基本上垂直于第二方向的第一方向彼此分离。 多个上柱可以形成在多个下支柱上。 多个上支柱具有比多个下支柱的宽度更小的宽度。 第一绝缘部件在多个下支柱中的每一个的侧壁上具有基本均匀的厚度。 第二绝缘部件可以形成在第一绝缘部分上以填充相邻的上部支柱之间的间隙。 字线可以形成在第二绝缘部分上,并且可以沿着第一方向在相邻的一对上柱的相对侧壁之间延伸。
    • 5. 发明申请
    • Semiconductor device and method of manufacturing the semiconductor device
    • 半导体装置及其制造方法
    • US20110183483A1
    • 2011-07-28
    • US13064628
    • 2011-04-05
    • Kang-Uk KimJae-Man YoonYong-Chul OhHui-Jung KimHyun-Woo ChungHyun-Gi Kim
    • Kang-Uk KimJae-Man YoonYong-Chul OhHui-Jung KimHyun-Woo ChungHyun-Gi Kim
    • H01L21/336
    • H01L21/823487H01L21/823456
    • In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.
    • 在半导体器件中,半导体器件可以包括第一有源结构,第一栅极绝缘层,第一栅极电极,第一杂质区域,第二杂质区域和接触结构。 第一有源结构可以包括在衬底的第一区域中的第一下部图案和第一下部图案上的第一上部图案。 第一栅极绝缘层可以形成在第一上部图案的侧壁上。 第一栅电极可以形成在第一栅极绝缘层上。 第一杂质区域可以形成在第一下部图案中。 第二杂质区域可以形成在第一上部图案中。 接触结构可以围绕第一上部图案的上表面和上侧壁包括第二杂质区域。 因此,可以降低接触结构和第二杂质区之间的接触电阻,并且可以提高接触结构的结构稳定性。
    • 6. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07943978B2
    • 2011-05-17
    • US12458262
    • 2009-07-07
    • Kang-Uk KimJae-Man YoonYong-Chul OhHui-Jung KimHyun-Woo ChungHyun-Gi Kim
    • Kang-Uk KimJae-Man YoonYong-Chul OhHui-Jung KimHyun-Woo ChungHyun-Gi Kim
    • H01L29/94
    • H01L21/823487H01L21/823456
    • In a semiconductor device, the semiconductor device may include a first active structure, a first gate insulation layer, a first gate electrode, a first impurity region, a second impurity region and a contact structure. The first active structure may include a first lower pattern in a first region of a substrate and a first upper pattern on the first lower pattern. The first gate insulation layer may be formed on a sidewall of the first upper pattern. The first gate electrode may be formed on the first gate insulation layer. The first impurity region may be formed in the first lower pattern. The second impurity region may be formed in the first upper pattern. The contact structure may surround an upper surface and an upper sidewall of the first upper pattern including the second impurity region. Accordingly, the contact resistance between the contact structure and the second impurity region may be decreased and structural stability of the contact structure may be improved.
    • 在半导体器件中,半导体器件可以包括第一有源结构,第一栅极绝缘层,第一栅极电极,第一杂质区域,第二杂质区域和接触结构。 第一有源结构可以包括在衬底的第一区域中的第一下部图案和第一下部图案上的第一上部图案。 第一栅极绝缘层可以形成在第一上部图案的侧壁上。 第一栅电极可以形成在第一栅极绝缘层上。 第一杂质区域可以形成在第一下部图案中。 第二杂质区域可以形成在第一上部图案中。 接触结构可以围绕第一上部图案的上表面和上侧壁包括第二杂质区域。 因此,可以降低接触结构和第二杂质区之间的接触电阻,并且可以提高接触结构的结构稳定性。