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1. 发明申请

US20090191681A1 NOR-TYPE FLASH MEMORY DEVICE WITH TWIN BIT CELL STRUCTURE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：具有双位晶胞结构的NOR型闪存存储器件及其制造方法
公开(公告)号：US20090191681A1
公开(公告)日：2009-07-30
申请号：US12418639
申请日：2009-04-06
申请人： Jae-Man YOON , Suk-kang SUNG , Dong-Gun PARK , Choong-Ho LEE , Tae-Yong KIM
发明人： Jae-Man YOON , Suk-kang SUNG , Dong-Gun PARK , Choong-Ho LEE , Tae-Yong KIM
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/7851
摘要： A NOR-type flash memory device comprises a plurality twin-bit memory cells arranged so that pairs of adjacent memory cells share a source/drain region and groups of four adjacent memory cells are electrically connected to each other by a single bitline contact.
摘要翻译： NOR型闪速存储器件包括多个双位存储器单元，其布置成使得相邻的存储单元对共享源极/漏极区域，并且四个相邻存储器单元的组通过单个位线接触彼此电连接。

2. 发明申请

US20090170271A1 TRANSISTOR AND METHOD OF FORMING THE SAME 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US20090170271A1
公开(公告)日：2009-07-02
申请号：US12397176
申请日：2009-03-03
申请人： Jae-Man YOON , Choong-Ho LEE , Dong-Gun PARK , Chul LEE
发明人： Jae-Man YOON , Choong-Ho LEE , Dong-Gun PARK , Chul LEE
IPC分类号： H01L21/426 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.
摘要翻译：根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。活性结构包括在源极/漏极区域下形成阻挡区的沟槽。栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

3. 发明申请

US20070090443A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FLOATING GATE AND RELATED DEVICE 有权
标题翻译：制备具有自对准浮选门的半导体器件及其相关器件的方法
公开(公告)号：US20070090443A1
公开(公告)日：2007-04-26
申请号：US11425205
申请日：2006-06-20
申请人： Byung-Yong CHOI , Choong-Ho LEE , Tae-Yong KIM , Dong-Gun PARK
发明人： Byung-Yong CHOI , Choong-Ho LEE , Tae-Yong KIM , Dong-Gun PARK
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device such as a flash memory device having a self-aligned floating gate and a method of fabricating the same is provided. An embodiment of the device includes an isolation layer defining a fin body is formed in a semiconductor substrate. The fin body has a portion protruding above the isolation layer. A sacrificial pattern is formed on the isolation layer. The sacrificial pattern has an opening self-aligned with the protruding portion of the fin body. The protruding fin body is exposed in the opening. An insulated floating gate pattern is formed to fill the opening. The sacrificial pattern is then removed. An inter-gate dielectric layer covering the floating gate pattern is formed. A control gate conductive layer is formed over the inter-gate dielectric layer. The control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern are patterned to form a control gate electrode crossing the fin body as well as the insulated floating gate interposed between the control gate electrode and the fin body.
摘要翻译：提供了诸如具有自对准浮动栅极的闪速存储器件及其制造方法的半导体器件。该器件的一个实施例包括在半导体衬底中形成限定翅片体的隔离层。翅片本体具有突出于隔离层上方的部分。在隔离层上形成牺牲图案。牺牲图案具有与翅片体的突出部分自对准的开口。突出的翅片体露出开口。形成绝缘浮栅图形以填充开口。然后去除牺牲图案。形成覆盖浮栅图案的栅极间介电层。在栅极间电介质层上形成控制栅极导电层。对控制栅极导电层，栅极间电介质层和浮置栅极图案进行图案化以形成跨越鳍体的控制栅电极以及插在控制栅电极和鳍体之间的绝缘浮栅。

4. 发明申请

US20070210368A1 GATE STRUCTURE AND METHOD OF FORMING THE GATE STRUCTURE, SEMICONDUCTOR DEVICE HAVING THE GATE STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：门结构和形成门结构的方法，具有门结构的半导体器件和制造半导体器件的方法
公开(公告)号：US20070210368A1
公开(公告)日：2007-09-13
申请号：US11683364
申请日：2007-03-07
申请人： Eun-Suk CHO , Jong-Jin LEE , Dong-Gun PARK , Jeong-Dong CHOE
发明人： Eun-Suk CHO , Jong-Jin LEE , Dong-Gun PARK , Jeong-Dong CHOE
IPC分类号： H01L21/3205 , H01L29/76
CPC分类号： H01L29/7885 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42332 , H01L29/7851 , H01L29/792
摘要： A gate structure in a semiconductor device includes a tunnel insulation layer disposed on a substrate, a first charge trapping layer disposed on the tunnel insulation layer, a second charge trapping layer disposed on the first charge trapping layer, a dielectric layer disposed to cover the second charge trapping layer, and a conductive layer pattern disposed on the dielectric layer. The first charge trapping layer includes charge trapping sites for storing charges therein. The second charge trapping layer includes nanocrystals. The semiconductor device including the gate structure may have a sufficiently wide programming/erasing window and an improved data retention capability.
摘要翻译：半导体器件中的栅极结构包括设置在衬底上的隧道绝缘层，设置在隧道绝缘层上的第一电荷俘获层，设置在第一电荷俘获层上的第二电荷俘获层，设置成覆盖第二电荷俘获层的电介质层电荷捕获层和设置在电介质层上的导电层图案。第一电荷俘获层包括用于在其中存储电荷的电荷俘获位置。第二电荷俘获层包括纳米晶体。包括栅极结构的半导体器件可以具有足够宽的编程/擦除窗口和改进的数据保持能力。

5. 发明申请

US20080296649A1 SEMICONDUCTOR DEVICE EMPLOYING BURIED INSULATING LAYER AND METHOD OF FABRICATING THE SAME 失效
标题翻译：采用绝缘绝缘层的半导体器件及其制造方法
公开(公告)号：US20080296649A1
公开(公告)日：2008-12-04
申请号：US11944260
申请日：2007-11-21
申请人： Chang-Woo OH , Dong-Gun PARK , Jeong-Dong CHOE , Kyoung-Hwan YEO
发明人： Chang-Woo OH , Dong-Gun PARK , Jeong-Dong CHOE , Kyoung-Hwan YEO
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/66651 , H01L27/10873 , H01L29/0653 , H01L29/66659
摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.
摘要翻译：半导体器件采用非对称埋层绝缘层及其制造方法。半导体器件包括下半导体衬底。上硅图案位于下半导体衬底上。上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。栅电极与上硅图案电绝缘，并且在沟道区域上相交。位线和单元电容器分别电连接到源极区域和漏极区域。掩埋绝缘层插入在漏区和下半导体衬底之间。掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

6. 发明申请

US20080145989A1 SEMICONDUCTOR DEVICE HAVING PARTIALLY INSULATED FIELD EFFECT TRANSISTOR (PiFET) AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：具有部分绝缘场效应晶体管（PiFET）的半导体器件及其制造方法
公开(公告)号：US20080145989A1
公开(公告)日：2008-06-19
申请号：US12040636
申请日：2008-02-29
申请人： Chang-Woo OH , Dong-Gun PARK , Jeong-Dong CHOE , Min-Sang KIM , Sung-Min KIM
发明人： Chang-Woo OH , Dong-Gun PARK , Jeong-Dong CHOE , Min-Sang KIM , Sung-Min KIM
IPC分类号： H01L29/06
CPC分类号： H01L21/823481 , H01L21/76283 , H01L29/1079 , H01L29/78
摘要： Embodiments of the invention include a partially insulated field effect transistor and a method of fabricating the same. According to some embodiments, a semiconductor substrate is formed by sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer. The sacrificial layer may be removed to form a buried gap region between the bottom semiconductor layer and the top semiconductor layer. Then, a transistor may be formed on the semiconductor substrate. The sacrificial layer may be a crystalline semiconductor formed by an epitaxial growth technology.
摘要翻译：本发明的实施例包括部分绝缘的场效应晶体管及其制造方法。根据一些实施例，通过顺序堆叠底部半导体层，牺牲层和顶部半导体层来形成半导体衬底。可以去除牺牲层以在底部半导体层和顶部半导体层之间形成掩埋间隙区域。然后，可以在半导体衬底上形成晶体管。牺牲层可以是通过外延生长技术形成的晶体半导体。

7. 发明申请

US20110108795A1 Molecular devices and methods of manufacturing the same 有权
公开(公告)号：US20110108795A1
公开(公告)日：2011-05-12
申请号：US12929118
申请日：2011-01-03
申请人： Dong-Won KIM , Dong-Gun PARK , Sung-Young LEE , Yang-Kyu CHOI , Lee-Eun YU
发明人： Dong-Won KIM , Dong-Gun PARK , Sung-Young LEE , Yang-Kyu CHOI , Lee-Eun YU
IPC分类号： H01L29/66
CPC分类号： H01L51/0595 , B82Y10/00 , G11C13/0014 , H01L51/102 , Y10T428/24
摘要： Molecular devices and methods of manufacturing the molecular device are provided. The molecular device may include a lower electrode on a substrate and a self-assembled monolayer on the lower electrode. After an upper electrode is formed on the self-assembled monolayer, the self-assembled monolayer may be removed to form a gap between the lower electrode and the upper electrode. A functional molecule having a functional group may be injected into the gap.

8. 发明申请

US20080032469A1 SEMICONDUCTOR DEVICES HAVING A FIELD EFFECT TRANSISTOR AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有场效应晶体管的半导体器件及其制造方法
公开(公告)号：US20080032469A1
公开(公告)日：2008-02-07
申请号：US11764751
申请日：2007-06-18
申请人： Chang-Woo OH , Dong-Gun PARK , Dong-Won KIM , Jeong-Dong CHOE
发明人： Chang-Woo OH , Dong-Gun PARK , Dong-Won KIM , Jeong-Dong CHOE
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/0653 , H01L29/66795 , H01L29/7851 , H01L29/78687 , Y10S438/933
摘要： A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.
摘要翻译：提供具有场效应晶体管的半导体器件及其形成方法。半导体器件优选地包括设置在衬底的预定区域上的器件有源图案。栅电极优选地跨过器件有源图案，由栅极绝缘层插入。支撑图案优选地插入在器件活性图案和基底之间。支撑图案可以设置在栅电极下方。填充绝缘图案优选地设置在装置活性图案和填充绝缘图案之间。填充绝缘图案可以设置在源极/漏极区域下方。栅电极下方的器件有源图案优选由具有比硅晶格宽的晶格宽度的应变硅形成。

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