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1. 发明授权

US5741738A Method of making corner protected shallow trench field effect transistor 失效
标题翻译：制造角保护浅沟槽场效应晶体管的方法
公开(公告)号：US5741738A
公开(公告)日：1998-04-21
申请号：US604283
申请日：1996-02-21
申请人： Jack A. Mandelman , Brian J. Machesney , Hing Wong , Michael M. Armacost , Pai-Hung Pan
发明人： Jack A. Mandelman , Brian J. Machesney , Hing Wong , Michael M. Armacost , Pai-Hung Pan
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.
摘要翻译：一种用于防止栅包绕和角寄生泄漏的半导体结构，包括具有平坦表面的半导体衬底。沟槽位于衬底中，沟槽具有侧壁。沟槽和表面的交点形成一个角落。介电线路沟槽的侧壁。并且，与拐角共同对准的拐角电介质在拐角处延伸超过衬底的最小尺寸距离。

2. 发明授权

US5521422A Corner protected shallow trench isolation device 失效
标题翻译：角保护浅沟隔离装置
公开(公告)号：US5521422A
公开(公告)日：1996-05-28
申请号：US348709
申请日：1994-12-02
申请人： Jack A. Mandelman , Brian J. Machesney , Hing Wong , Michael D. Armacost , Pai-Hung Pan
发明人： Jack A. Mandelman , Brian J. Machesney , Hing Wong , Michael D. Armacost , Pai-Hung Pan
IPC分类号： H01L21/762 , H01L29/00
CPC分类号： H01L21/76224
摘要： A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.
摘要翻译：一种用于防止栅包绕和角寄生泄漏的半导体结构，包括具有平坦表面的半导体衬底。沟槽位于衬底中，沟槽具有侧壁。沟槽和表面的交点形成一个角落。介电线路沟槽的侧壁。并且，与拐角共同对准的拐角电介质在拐角处延伸超过衬底的最小尺寸距离。

3. 发明授权

US5587604A Contacted body silicon-on-insulator field effect transistor 失效
标题翻译：接触体上绝缘体上的场效应晶体管
公开(公告)号：US5587604A
公开(公告)日：1996-12-24
申请号：US310691
申请日：1994-09-22
申请人： Brian J. Machesney , Jack A. Mandelman , Edward J. Nowak
发明人： Brian J. Machesney , Jack A. Mandelman , Edward J. Nowak
IPC分类号： H01L29/786 , H01L27/12 , H01L27/01
CPC分类号： H01L27/1203 , H01L2924/0002 , Y10S148/15 , Y10S438/98
摘要： Structures and methods are presented for forming a body-substrate connector for an SOI FET. The connector is formed substantially co-aligned with the gate conductor on a side of the device that does not interfere with source and drain. The body is thus held close to the substrate potential and the connector provides a path for majority carriers to quickly leave the body. By contacting the body of the SOI MOSFET device in a manner that does not perturb the charge imaged by the gate, parasitic bipolar effects are eliminated while maintaining the desirable attributes of SOI MOSFET devices, such as low substrate bias sensitivity and steep sub-threshold slope. By forming the connector substantially co-aligned with the gate conductor the connection uses little or no surface area.
摘要翻译：提出了用于形成用于SOI FET的体衬底连接器的结构和方法。该连接器在不干扰源极和漏极的装置的一侧基本上与栅极导体共同对准。因此，本体保持靠近基底电位，并且连接器为多数载体快速离开身体提供了路径。通过以不扰乱由栅极成像的电荷的方式接触SOI MOSFET器件的主体，消除寄生双极效应，同时保持SOI MOSFET器件的期望属性，例如低衬底偏置灵敏度和陡峭的次阈值斜率。通过形成与栅极导体基本上共同对准的连接器，连接使用很少或没有表面积。

4. 发明授权

US5173439A Forming wide dielectric-filled isolation trenches in semi-conductors 失效
标题翻译：在半导体中形成宽电介质填充的隔离沟槽
公开(公告)号：US5173439A
公开(公告)日：1992-12-22
申请号：US679568
申请日：1991-04-02
申请人： Somanath Dash , Michael L. Kerbaugh , Charles W. Koburger, III , Brian J. Machesney , Nitin B. Parekh
发明人： Somanath Dash , Michael L. Kerbaugh , Charles W. Koburger, III , Brian J. Machesney , Nitin B. Parekh
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/762
CPC分类号： H01L21/02063 , H01L21/3105 , H01L21/31053 , H01L21/31116 , H01L21/76229
摘要： A method of forming a planarized dielectric filled wide shallow trench in a semi-conductor substrate is provided. A layer of etch stop such as Si.sub.3 N.sub.4 is deposited onto the semi-conductor substrate, and wide trenches are formed through the Si.sub.3 N.sub.4 into the substrate by conventional RIE. The surface of the substrate including the trenches have formed thereon a SiO.sub.2 coating, conforming to the surface of the substrate. A layer of etch resistant material such as polysilicon is deposited onto the SiO.sub.2 material. The polysilicon outside the width of the trenches is then removed by chemical-mechanical polishing to expose the SiO.sub.2 there below, while leaving the SiO.sub.2 above the trenches covered with polysilicon. The exposed SiO.sub.2 is then RIE etched down to the Si.sub.3 N.sub.4, leaving a plug of SiO.sub.2 capped with the etch resistant polysilicon over each trench. These plugs are then removed by mechanical polishing down to the Si.sub.3 N.sub.4, to provide a planarized upper surface of SiO.sub.2 and Si.sub.3 N.sub.4 on the top of the substrate. The invention also is useful in forming planarized surfaces on substrates having trenches filled with conductive material.
摘要翻译：提供了一种在半导体衬底中形成平坦化介质填充的宽浅沟槽的方法。将诸如Si 3 N 4的蚀刻停止层沉积到半导体衬底上，并且通过常规RIE通过Si 3 N 4形成宽的沟槽进入衬底。包括沟槽的衬底的表面在其上形成符合衬底表面的SiO 2涂层。将诸如多晶硅的耐蚀刻材料层沉积到SiO 2材料上。然后通过化学机械抛光去除沟槽宽度外的多晶硅，以在下面暴露出SiO 2，同时在覆盖有多晶硅的沟槽上留下SiO 2。然后将暴露的SiO 2 RIE蚀刻到Si 3 N 4上，在每个沟槽上留下带有耐蚀刻多晶硅的SiO 2塞。然后通过机械抛光除去Si 3 N 4，从而在衬底的顶部提供SiO 2和Si 3 N 4的平坦化上表面。本发明还可用于在具有填充有导电材料的沟槽的衬底上形成平坦化表面。

5. 发明授权

US5466636A Method of forming borderless contacts using a removable mandrel 失效
标题翻译：使用可移动心轴形成无边界触点的方法
公开(公告)号：US5466636A
公开(公告)日：1995-11-14
申请号：US946993
申请日：1992-09-17
申请人： John E. Cronin , Carter W. Kaanta , Donald M. Kenney , Michael L. Kerbaugh , Howard S. Landis , Brian J. Machesney , Paul Parries , Rosemary A. Previti-Kelly , John F. Rembetski
发明人： John E. Cronin , Carter W. Kaanta , Donald M. Kenney , Michael L. Kerbaugh , Howard S. Landis , Brian J. Machesney , Paul Parries , Rosemary A. Previti-Kelly , John F. Rembetski
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L29/417 , H01L21/44
CPC分类号： H01L27/10861 , H01L21/76838 , H01L21/76897 , H01L29/41766 , Y10S438/943
摘要： A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is made from a material that will etch at a faster rate than the barrier layer so as to permit the formation of openings in the mandrel to be stopped on the barrier layer without penetrating such layer. After depositing a contact (130) in a first opening (120) formed in the mandrel, a second opening (140) is formed and a second contact (170) is deposited therein. Thereafter, the mandrel is removed and replaced with a layer of solid dielectric material (180).
摘要翻译：一种用于使用可移除心轴（110）形成无边界触点（130,170,172）的半导体制造工艺。该方法包括将心轴沉积在设计成保护形成在基底（24）上的下面的结构（40）的下面的阻挡层（100）上。心轴由将以比阻挡层更快的速度蚀刻的材料制成，以允许心轴中的开口形成停止在阻挡层上而不穿透该层。在将形成在心轴中的第一开口（120）中的接触（130）沉积之后，形成第二开口（140），并且在其中沉积第二接触（170）。此后，移去心轴并用一层固体电介质材料（180）代替。

6. 发明授权

US5213655A Device and method for detecting an end point in polishing operation 失效
标题翻译：用于检测抛光操作中的终点的装置和方法
公开(公告)号：US5213655A
公开(公告)日：1993-05-25
申请号：US844439
申请日：1992-03-02
申请人： Michael A. Leach , Brian J. Machesney , Edward J. Nowak
发明人： Michael A. Leach , Brian J. Machesney , Edward J. Nowak
IPC分类号： B24B37/013 , H01L21/302
CPC分类号： B24B37/013 , G01B7/10 , G01B7/105
摘要： The present invention relates to a method and apparatus for remotely detecting impedance. It is specifically adapted for use on a polishing machine wherein the end point of polishing for removing a surface layer during the processing of semiconductor substrates is detected. A first, or stationary coil having a high permeability core is wound having an air gap and an AC voltage is applied to the stationary coil to provide a magnetic flux in the air gap. A second coil is mounted for rotation on the polishing table, in a position to periodically pass through the air gap of the stationary coil as the table rotates. The second coil is connected at its opposite ends to contacts which are embedded in the surface of the polishing wheel. The contacts are positioned to engage the surface of the substrate which is being polished and provide a load on the second or rotating coil. The rotating coil, when it is in the air gap of the stationary coil, will perturb the flux field therein as a function of the resistance of the load caused by the contacts contacting either a conducting surface or a non-conducting surface. This perturbance of the flux field is measured as a change in the induced voltage in the stationary coil which in turn is converted to a signal which is processed to indicate the end point of polishing, the end point being when a metallic layer has been removed to expose a dielectric layer therebeneath or, conversely, when a dielectric layer has been removed to expose a metallic layer therebeneath.
摘要翻译：本发明涉及用于远程检测阻抗的方法和装置。它特别适用于抛光机，其中检测在半导体衬底的处理期间用于去除表面层的抛光终点。具有高磁导率芯的第一或固定线圈缠绕有气隙并且将AC电压施加到固定线圈以在气隙中提供磁通量。第二线圈安装成在研磨台上旋转，以便在桌子旋转时周期性地通过固定线圈的气隙的位置。第二线圈在其相对端连接到嵌入抛光轮表面的触点。触点定位成接合被抛光的基板的表面，并在第二或旋转的线圈上提供负载。当旋转线圈处于固定线圈的空气隙中时，其将作为由触点接触任何导电表面或不导电表面引起的负载的电阻的函数扰乱其中的磁通场。测量磁通场的扰动是作为固定线圈中的感应电压的变化而被测量的，该感应电压又被转换成被处理以指示抛光的终点的信号，终点是当金属层被去除时的终点在其下面露出介电层，或者相反地，当电介质层被去除以暴露其下面的金属层时。

7. 发明授权

US5132617A Method of measuring changes in impedance of a variable impedance load by disposing an impedance connected coil within the air gap of a magnetic core 失效
标题翻译：通过在磁芯的空气隙中处理阻抗连接的线圈来测量可变阻抗负载变化的方法
公开(公告)号：US5132617A
公开(公告)日：1992-07-21
申请号：US525352
申请日：1990-05-16
申请人： Michael A. Leach , Brian J. Machesney , Edward J. Nowak
发明人： Michael A. Leach , Brian J. Machesney , Edward J. Nowak
IPC分类号： H01L21/304 , B24B37/013 , G01B7/14 , H01L21/302 , H01L21/66
CPC分类号： B24B37/013 , G01B7/10 , G01B7/105
摘要： The present invention relates to a method and apparatus for remotely detecting impedance. It is specifically adapted for use on a polishing machine wherein the end point of polishing for removing a surface layer during the processing of semiconductor substrates is detected. A first, or stationary coil having a high permeability core is wound having an air gap and an AC voltage is applied to the stationary coil to provide a magnetic flux in the air gap. A second coil is mounted for rotation on the polishing table, in a position to periodically pass through the air gap of the stationary coil as the table rotates. The second coil is connected at its opposite ends to contacts which are embedded in the surface of the polishing wheel. The contacts are positioned to engage the surface of the substrate which is being polished and provide a load on the second or rotating coil. The rotating coil, when it is in the air gap of the stationary coil, will perturb the flux field therein as a function of the resistance of the load caused by the contacts contacting either a conducting surface or a non-conducting surface. This perturbance of the flux field is measured as a change in the induced voltage in the stationary coil which in turn is converted to a signal which is processed to indicate the end point of polishing, the end point being when a metallic layer has been removed to expose a dielectric layer therebeneath or, conversely, when a dielectric layer has been removed to expose a metallic layer therebeneath.

8. 发明授权

US4728623A Fabrication method for forming a self-aligned contact window and connection in an epitaxial layer and device structures employing the method 失效
标题翻译：用于在外延层中形成自对准接触窗和连接的制造方法以及采用该方法的器件结构
公开(公告)号：US4728623A
公开(公告)日：1988-03-01
申请号：US915310
申请日：1986-10-03
申请人： Nicky C. Lu , Brian J. Machesney
发明人： Nicky C. Lu , Brian J. Machesney
IPC分类号： H01L27/04 , H01L21/20 , H01L21/205 , H01L21/74 , H01L21/763 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70
CPC分类号： H01L21/743 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/763 , H01L27/10832
摘要： A fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands which forms a self-aligned contact window in the epitaxial layer.Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor formed in monocrystalline silicon stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process. The invention can be further applied to other device structures using the described principles, and more specifically to an inverter structure having the driver device stacked over the load-resistor as another example, which can be used as a basic building circuit unit for logic circuits and static-RAM cell.

9. 发明授权

US5242524A Device for detecting an end point in polishing operations 失效
标题翻译：用于检测抛光操作中的终点的装置
公开(公告)号：US5242524A
公开(公告)日：1993-09-07
申请号：US12056
申请日：1993-02-01
申请人： Michael A. Leach , Brian J. Machesney , Edward J. Nowak
发明人： Michael A. Leach , Brian J. Machesney , Edward J. Nowak
IPC分类号： B24B37/013 , H01L21/302
CPC分类号： B24B37/013 , G01B7/10 , G01B7/105
摘要： The present invention relates to an apparatus for remotely detecting impedance adapted for use on a polishing machine wherein the end point of polishing for removing a surface layer during the processing of semiconductor substrates is detected. A first stationary coil having a high permeability core is wound having an air gap and an AC voltage is applied to the stationary coil to provide a magnetic flux in the air gap. A second coil is mounted for rotation on the polishing table, in a position to periodically pass through the air gap of the stationary coil as the table rotates. The second coil is connected at its opposite ends to contacts which are embedded in the surface of the polishing wheel. The contacts are positioned to engage the surface of the substrate being polished and provide a load on the second rotating coil when it is in the air gap of the stationary coil, will perturb the flux field therein as a function of the resistance of the load caused by the contacts contacting either a conducting surface or a non-conducting surface. This perturbance of the flux field is measured as a change in the induced voltage in the stationary coil which is converted to a signal processed to indicate the end point of polishing, the end point being when a metallic layer has been removed to expose a dielectric layer or when a dielectric layer has been removed to expose a metallic layer.
摘要翻译：本发明涉及一种用于远程检测适用于抛光机器的阻抗的装置，其中检测在半导体衬底的处理期间用于去除表面层的抛光终点。具有高磁导率芯的第一固定线圈缠绕有气隙并且将AC电压施加到固定线圈以在气隙中提供磁通量。第二线圈安装成在研磨台上旋转，以便在桌子旋转时周期性地通过固定线圈的气隙的位置。第二线圈在其相对端连接到嵌入抛光轮表面的触点。接触件被定位成接合正被抛光的基板的表面，并且当其处于固定线圈的气隙中时，在第二旋转线圈上提供负载将根据负载的电阻而扰乱其中的磁通场通过触点接触导电表面或非导电表面。磁通场的这种扰动被测量为固定线圈中的感应电压的变化，其被转换为处理以指示抛光的终点的信号，终点是当金属层被去除以暴露电介质层或者当电介质层被去除以暴露金属层时。

10. 发明授权

US4983544A Silicide bridge contact process 失效
标题翻译：硅化物桥接触过程
公开(公告)号：US4983544A
公开(公告)日：1991-01-08
申请号：US920471
申请日：1986-10-20
申请人： Nicky C. Lu , Brian J. Machesney , Rick L. Mohler , Glen L. Miles , Chung-Yu Ting , Stephen D. Warley
发明人： Nicky C. Lu , Brian J. Machesney , Rick L. Mohler , Glen L. Miles , Chung-Yu Ting , Stephen D. Warley
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/482 , H01L23/52 , H01L29/45
CPC分类号： H01L21/76895 , H01L21/76886 , H01L23/4821 , H01L29/456 , H01L2924/0002 , Y10S148/019 , Y10S148/147
摘要： A method of forming a bridge contact between a source diffusion region of a transfer gate FET and a polysilicon-filled trench storage capacitor electrodes of the FET. A layer of titanium is evaporated at a temperature of approximately 370.degree. C., so that the titanium has a substantially columnar grain structure and a minimum of matrix material. The bottom portions of the columnar grains have a lateral length that approximates the lateral length of the dielectric separating the source diffusion from the poly-filled trench. Thus, upon sintering at 700.degree. C. in an N.sub.2 atmosphere, titanium silicide will form over all exposed silicon regions as well as the dielectric, without shorting the FET electrodes together.
摘要翻译：在传输栅极FET的源极扩散区域和FET的多晶硅填充的沟槽存储电容器电极之间形成桥接触的方法。在约370℃的温度下蒸发一层钛，使得钛具有基本上柱状的晶粒结构和最小的基体材料。柱状晶粒的底部具有近似于将源极扩散与多孔填充沟槽分离的介质的横向长度的横向长度。因此，在N 2气氛中在700℃烧结时，在所有暴露的硅区域和电介质上形成硅化钛，而不会将FET电极短路在一起。

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