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1. 发明授权

US07956658B2 Digital lock detector and frequency synthesizer using the same 有权
标题翻译：数字锁定检测器和频率合成器使用相同
公开(公告)号：US07956658B2
公开(公告)日：2011-06-07
申请号：US12607395
申请日：2009-10-28
申请人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

2. 发明申请

US20100271072A1 DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME 有权
标题翻译：使用数字锁定检测器和频率合成器
公开(公告)号：US20100271072A1
公开(公告)日：2010-10-28
申请号：US12607395
申请日：2009-10-28
申请人： Ja Yol LEE , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol LEE , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03K5/22 , H03B21/00
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

3. 发明授权

US08013641B1 Frequency synthesizer including a digital lock detector 有权
标题翻译：频率合成器包括数字锁定检测器
公开(公告)号：US08013641B1
公开(公告)日：2011-09-06
申请号：US13098332
申请日：2011-04-29
申请人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03B21/00
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

4. 发明授权

US08031009B2 Frequency calibration loop circuit 失效
标题翻译：频率校准回路电路
公开(公告)号：US08031009B2
公开(公告)日：2011-10-04
申请号：US12581105
申请日：2009-10-16
申请人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
发明人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/085 , H03L7/095 , H03L7/18 , H03L7/081
CPC分类号： H03L7/181 , H03L2207/50 , Y10S331/02
摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.
摘要翻译：一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数）包括：振荡器，根据控制值调整振荡信号的振荡频率; 可编程分频器，根据分频比除以振荡信号，输出分频信号; 计数针对参考信号的一个周期的分频信号的时钟数，以输出计数值; 以及频率检测器，通过从参考比较值中减去计数值来获得控制值，其中通过将频率通道字（FCW）指令值除以可编程分频器的最小分频比来获得参考比较值。

5. 发明申请

US20100134192A1 FREQUENCY CALIBRATION LOOP CIRCUIT 失效
标题翻译：频率校准环路
公开(公告)号：US20100134192A1
公开(公告)日：2010-06-03
申请号：US12581105
申请日：2009-10-16
申请人： Byung Hun MIN , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
发明人： Byung Hun MIN , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/00
CPC分类号： H03L7/181 , H03L2207/50 , Y10S331/02
摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting a oscillation frequency according to control value; a programmable divider dividing the oscillation frequency according to a division ratio; a counter counting the number of clocks of the divided frequency by using a reference frequency; and a frequency detector outputting a value obtained by subtracting the number of the counted clocks from a reference comparison value, a value obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider, as the control value of the oscillator.
摘要翻译：一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数）包括：振荡器根据控制值调节振荡频率; 一个可编程除法器根据分频比划分振荡频率; 通过使用参考频率对分频频率的时钟数进行计数的计数器; 输出通过从参考比较值中减去计数时钟数而得到的值的频率检测器，通过将频率通道字（FCW）指令值除以可编程分压器的最小分频比而获得的值作为控制值的振荡器。

6. 发明授权

US07626476B2 Multi-metal coplanar waveguide 有权
标题翻译：多金属共面波导
公开(公告)号：US07626476B2
公开(公告)日：2009-12-01
申请号：US11690219
申请日：2007-03-23
申请人： Cheon Soo Kim , Myung Shin Kwak , Seong Do Kim , Mun Yang Park , Hyun Kyu Yu , Hee Bum Jung
发明人： Cheon Soo Kim , Myung Shin Kwak , Seong Do Kim , Mun Yang Park , Hyun Kyu Yu , Hee Bum Jung
IPC分类号： H01P3/08
CPC分类号： H01P3/003
摘要： A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.
摘要翻译：提供了一种使用多层互连CMOS技术的共面波导CPW。在包括设置在基板上的层间绝缘体的CPW中，设置在层间绝缘体上的金属多层和最下层的接地线的接地线 - 信号线 - 由最上层金属层形成的接地线连接到最上层的地线，中间金属层被设计成逐渐增加或减小宽度或不均匀，以便使超高频率扩展的面积最大化，由此最小化CPW损耗并最大化慢波效应。结果，可以提高超高频电路的性能并使电路小型化。

7. 发明申请

US20120161832A1 FRACTIONAL DIGITAL PLL WITH ANALOG PHASE ERROR COMPENSATOR 有权
标题翻译：具有模拟相位误差补偿器的数字数字锁相环
公开(公告)号：US20120161832A1
公开(公告)日：2012-06-28
申请号：US13310581
申请日：2011-12-02
申请人： Ja Yol Lee , Seong-Do Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seong-Do Kim , Hyun Kyu Yu
IPC分类号： H03L7/08
CPC分类号： H03L7/0802 , H03L7/085 , H03L2207/50
摘要： Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.
摘要翻译：公开了具有模拟相位误差补偿器的分数字数字锁相环。具有模拟相位误差补偿器的数字锁相环可以通过模拟相位误差补偿器进行分数相位误差检测和补偿，从而降低功耗，功耗噪声和瞬态电流噪声，同时提高相位误差检测分辨率。

8. 发明授权

US08060020B2 Apparatus and method for removing interference signal using selective frequency phase converter 有权
标题翻译：使用选择性频率相位转换器去除干扰信号的装置和方法
公开(公告)号：US08060020B2
公开(公告)日：2011-11-15
申请号：US12628684
申请日：2009-12-01
申请人： Seong Do Kim , Ja Yol Lee , Jae Hoon Shim , Hyun Kyu Yu
发明人： Seong Do Kim , Ja Yol Lee , Jae Hoon Shim , Hyun Kyu Yu
IPC分类号： H04B1/00
CPC分类号： H04B1/123
摘要： An apparatus and method for removing an interference signal using a selective frequency phase converter are disclosed. The apparatus for removing an interference signal using a selective frequency phase converter includes: a first phase converter configured to convert a phase of a received RF signal to differentially output first and second signals having a phase difference of 180° from each other; a second phase converter configured to receive the first signal and selectively convert the phase of a particular frequency band; a third phase converter configured to receive the second signal and selectively convert the phase of a particular frequency band; a timing controller configured to correct a signal delay time between the output from the second phase converter and that of the third phase converter; and an adder configured to add an output from the second phase converter and an output from the third phase converter, wherein the second and third phase converters phase-convert the first and second signals such that the phases of the signals of the particular frequency bands do not have a phase difference of 180° from each other.
摘要翻译：公开了一种使用选择性频率相位变换器去除干扰信号的装置和方法。使用选择性频率相位变换器去除干扰信号的装置包括：第一相位转换器，被配置为将接收的RF信号的相位转换为差分地输出具有彼此相差180°的第一和第二信号; 第二相转换器，被配置为接收第一信号并选择性地转换特定频带的相位; 配置为接收所述第二信号并选择性地转换特定频带的相位的第三相位转换器; 定时控制器，被配置为校正来自第二相位转换器的输出和第三相位转换器的输出之间的信号延迟时间; 以及加法器，被配置为将来自第二相位转换器的输出和来自第三相位转换器的输出相加，其中第二和第三相位转换器对第一和第二信号进行相位转换，使得特定频带的信号的相位做彼此之间没有180°的相位差。

9. 发明申请

US20100134195A1 CAPACITOR HAVING VARIABLE CAPACITANCE AND DIGITALLY CONTROLLED OSCILLATOR INCLUDING THE SAME 审中-公开
标题翻译：具有可变电容的电容器和包括其的数字控制振荡器
公开(公告)号：US20100134195A1
公开(公告)日：2010-06-03
申请号：US12629742
申请日：2009-12-02
申请人： Ja Yol LEE , Byung Hun Min , Seong Do Kim , Hyun Kyu Yu
发明人： Ja Yol LEE , Byung Hun Min , Seong Do Kim , Hyun Kyu Yu
IPC分类号： H03B5/12 , H01L27/06
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1265
摘要： There is provided a capacitor having variable capacitance, which forms different capacitances according to a control signal by applying a switch to a metal-oxide-metal (MOM) structure plate capacitor using a CMOS process. The capacitor includes a stack structure including a plurality of metal layers including a first metal layer, and a plurality of dielectric layers respectively interposed between the plurality of metal layers, and a switch part including at least one switch having one side connected to at least one metal layer among the plurality of metal layers other than the first metal layer. The first metal layer and the other side of the switch serve as both terminals of the capacitor, and at least two capacitances are provided between both terminals of the capacitor upon controlling a short/open of the switch.
摘要翻译：提供具有可变电容的电容器，其通过使用CMOS工艺将开关施加到金属氧化物金属（MOM）结构板电容器上，根据控制信号形成不同的电容。电容器包括堆叠结构，其包括多个金属层，包括第一金属层和分别介于多个金属层之间的多个电介质层，以及开关部分，其包括至少一个开关，该开关的一侧连接至至少一个除了第一金属层之外的多个金属层中的金属层。开关的第一金属层和另一侧用作电容器的两端，并且在控制开关的短路/断开时，至少两个电容设置在电容器的两个端子之间。

10. 发明申请

US20110148490A1 TIME-TO-DIGITAL CONVERTER AND ALL DIGITAL PHASE-LOCKED LOOP INCLUDING THE SAME 有权
标题翻译：时数转换器和所有数字相位锁定环路
公开(公告)号：US20110148490A1
公开(公告)日：2011-06-23
申请号：US12956498
申请日：2010-11-30
申请人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
IPC分类号： H03L7/08 , H03M1/50
CPC分类号： H03L7/095 , G04F10/005 , H03L7/085 , H03L7/103 , H03L2207/50
摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.
摘要翻译：全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出来改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

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