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1. 发明授权

US07626476B2 Multi-metal coplanar waveguide 有权
标题翻译：多金属共面波导
公开(公告)号：US07626476B2
公开(公告)日：2009-12-01
申请号：US11690219
申请日：2007-03-23
申请人： Cheon Soo Kim , Myung Shin Kwak , Seong Do Kim , Mun Yang Park , Hyun Kyu Yu , Hee Bum Jung
发明人： Cheon Soo Kim , Myung Shin Kwak , Seong Do Kim , Mun Yang Park , Hyun Kyu Yu , Hee Bum Jung
IPC分类号： H01P3/08
CPC分类号： H01P3/003
摘要： A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.
摘要翻译：提供了一种使用多层互连CMOS技术的共面波导CPW。在包括设置在基板上的层间绝缘体的CPW中，设置在层间绝缘体上的金属多层和最下层的接地线的接地线 - 信号线 - 由最上层金属层形成的接地线连接到最上层的地线，中间金属层被设计成逐渐增加或减小宽度或不均匀，以便使超高频率扩展的面积最大化，由此最小化CPW损耗并最大化慢波效应。结果，可以提高超高频电路的性能并使电路小型化。

2. 发明授权

US08013641B1 Frequency synthesizer including a digital lock detector 有权
标题翻译：频率合成器包括数字锁定检测器
公开(公告)号：US08013641B1
公开(公告)日：2011-09-06
申请号：US13098332
申请日：2011-04-29
申请人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03B21/00
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

3. 发明授权

US07956658B2 Digital lock detector and frequency synthesizer using the same 有权
标题翻译：数字锁定检测器和频率合成器使用相同
公开(公告)号：US07956658B2
公开(公告)日：2011-06-07
申请号：US12607395
申请日：2009-10-28
申请人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

4. 发明申请

US20100271072A1 DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME 有权
标题翻译：使用数字锁定检测器和频率合成器
公开(公告)号：US20100271072A1
公开(公告)日：2010-10-28
申请号：US12607395
申请日：2009-10-28
申请人： Ja Yol LEE , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
发明人： Ja Yol LEE , Seong Do Kim , Mun Yang Park , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03K5/22 , H03B21/00
CPC分类号： H03L7/16 , H03L7/095 , H03L7/099 , H03L7/103 , H03L2207/50
摘要： There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
摘要翻译：提供了数字锁定检测器和使用该锁定检测器的频率合成器。数字锁定检测器包括：接收多个控制位的比较器单元，并产生一个位信号以注意多个控制位的锁定状态; 延迟单元块，其基于所述位信号生成多个延迟信号，并通过组合所述位信号和所述多个延迟信号来输出时钟信号; 以及检测单元，其检测所述时钟信号的移位时间，并根据所述检测结果生成锁定指示信号。

5. 发明授权

US06992366B2 Stacked variable inductor 有权
标题翻译：堆叠式可变电感
公开(公告)号：US06992366B2
公开(公告)日：2006-01-31
申请号：US10671637
申请日：2003-09-29
申请人： Cheon Soo Kim , Pil Jae Park , Mun Yang Park , Hyun Kyu Yu
发明人： Cheon Soo Kim , Pil Jae Park , Mun Yang Park , Hyun Kyu Yu
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L28/10 , H01F17/0013 , H01F21/12 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed is a stacked variable inductors manufactured by stacking M (M≧2) metal layers on a semiconductor substrate, and provides stacked variable inductors comprising, 1 to N inductors continuously connected in serial, wherein each of said inductors is formed on N (N≦M) metal layers that are different each other; first and second ports each connected to the highest positioned inductor and to the lowest positioned inductor among said 1 to N inductors; and at least one MOSFET, and wherein one terminal of at least one MOSFET is connected to one of the first and second ports, and the other one is connected to one of adjacent terminals connected in serial between 1 to N inductors.
摘要翻译：公开了一种通过在半导体衬底上堆叠M（M> = 2）金属层而制造的层叠可变电感器，并提供包括串联连续连接的1至N个电感器的堆叠可变电感器，其中每个所述电感器形成在N <= M）彼此不同的金属层; 所述1至N电感器中的第一和第二端口各自连接到最高位置的电感器和最低位置的电感器; 和至少一个MOSFET，并且其中至少一个MOSFET的一个端子连接到所述第一和第二端口中的一个，并且另一个连接到串联连接在1至N个电感器之间的相邻端子之一。

6. 发明授权

US08031009B2 Frequency calibration loop circuit 失效
标题翻译：频率校准回路电路
公开(公告)号：US08031009B2
公开(公告)日：2011-10-04
申请号：US12581105
申请日：2009-10-16
申请人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
发明人： Byung Hun Min , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/085 , H03L7/095 , H03L7/18 , H03L7/081
CPC分类号： H03L7/181 , H03L2207/50 , Y10S331/02
摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.
摘要翻译：一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数）包括：振荡器，根据控制值调整振荡信号的振荡频率; 可编程分频器，根据分频比除以振荡信号，输出分频信号; 计数针对参考信号的一个周期的分频信号的时钟数，以输出计数值; 以及频率检测器，通过从参考比较值中减去计数值来获得控制值，其中通过将频率通道字（FCW）指令值除以可编程分频器的最小分频比来获得参考比较值。

7. 发明申请

US20100134192A1 FREQUENCY CALIBRATION LOOP CIRCUIT 失效
标题翻译：频率校准环路
公开(公告)号：US20100134192A1
公开(公告)日：2010-06-03
申请号：US12581105
申请日：2009-10-16
申请人： Byung Hun MIN , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
发明人： Byung Hun MIN , Ja Yol Lee , Seong Do Kim , Cheon Soo Kim , Hyun Kyu Yu
IPC分类号： H03L7/00
CPC分类号： H03L7/181 , H03L2207/50 , Y10S331/02
摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting a oscillation frequency according to control value; a programmable divider dividing the oscillation frequency according to a division ratio; a counter counting the number of clocks of the divided frequency by using a reference frequency; and a frequency detector outputting a value obtained by subtracting the number of the counted clocks from a reference comparison value, a value obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider, as the control value of the oscillator.
摘要翻译：一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数）包括：振荡器根据控制值调节振荡频率; 一个可编程除法器根据分频比划分振荡频率; 通过使用参考频率对分频频率的时钟数进行计数的计数器; 输出通过从参考比较值中减去计数时钟数而得到的值的频率检测器，通过将频率通道字（FCW）指令值除以可编程分压器的最小分频比而获得的值作为控制值的振荡器。

8. 发明授权

US08542773B2 Digital RF converter, digital RF modulator and transmitter including the same 有权
标题翻译：数字RF转换器，数字RF调制器和发射机包括相同
公开(公告)号：US08542773B2
公开(公告)日：2013-09-24
申请号：US12968731
申请日：2010-12-15
申请人： Hyun Kyu Yu , Jang Hong Choi , Hyun Ho Boo , Pil Jae Park , Mun Yang Park , Seong Do Kim , Sun Bo Shim , Song Cheol Hong
发明人： Hyun Kyu Yu , Jang Hong Choi , Hyun Ho Boo , Pil Jae Park , Mun Yang Park , Seong Do Kim , Sun Bo Shim , Song Cheol Hong
IPC分类号： H04L27/20 , H03C3/00 , H03M3/00 , H03M1/66
CPC分类号： H03M1/68 , H03M1/687 , H03M1/745 , H03M1/747 , H03M3/50
摘要： A digital RF converter, a digital RF modulator, and a transmitter are provided. The digital RF converter includes a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed, a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed, and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.
摘要翻译：提供数字RF转换器，数字RF调制器和发射器。该数字RF转换器包括一个Δ-Σ调制比特（DSMB）子块，其以第一采样速度在输入信号之间产生对应于最低有效n比特的当前幅度，最低有效位（LSB）子块，以低于第一采样速度的第二采样速度产生对应于输入信号中的中间k位的电流幅度，以及最高有效位（MSB）子块，其产生对应于最高有效m位的当前幅度以第二采样速度输入信号。

9. 发明授权

US06615398B2 Method for dividing ROM and DDFS using the same method 有权
公开(公告)号：US06615398B2
公开(公告)日：2003-09-02
申请号：US10017315
申请日：2001-12-18
申请人： Hyun Kyu Yu , Seon-Ho Han , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Lee-Sup Kim , Ki-Hyuk Sung , Byung-Do Yang , Young-Jun Kim
发明人： Hyun Kyu Yu , Seon-Ho Han , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Lee-Sup Kim , Ki-Hyuk Sung , Byung-Do Yang , Young-Jun Kim
IPC分类号： G06F1750
CPC分类号： G06F1/0356 , G06F1/0328 , G06F2101/04 , G11C17/00
摘要： The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e., coarse-quantized ROM, coarse-error ROM, fine-quantized ROM and fine-error ROM.

10. 发明授权

US06605996B2 Automatically gain controllable linear differential amplifier using variable degeneration resistor 有权
标题翻译：使用可变退化电阻自动增益可控线性差分放大器
公开(公告)号：US06605996B2
公开(公告)日：2003-08-12
申请号：US10039542
申请日：2001-12-31
申请人： Hyun Kyu Yu , Sang-Gug Lee , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Seon-Ho Han , Nam-Soo Kim
发明人： Hyun Kyu Yu , Sang-Gug Lee , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Seon-Ho Han , Nam-Soo Kim
IPC分类号： H03F345
CPC分类号： H03G1/007 , H03F3/45179 , H03F2203/45492 , H03G1/0023
摘要： An automatically gain controllable linear differential amplifier using a variable degeneration resistor is disclosed. The linear differential amplifier includes an input end, a bias current source, a load unit, a first MOS transistor and a second MOS transistor. The linear differential amplifiers of the present invention can control an amplifying gain according to an input signal and improve linearity IIP3 without needing additional power consumption caused by improving the linearity. The automatically gain controllable linear differential amplifier uses NMOS/PMOS transistor so an integration process of the amplifier can be implemented more conveniently and efficiently.
摘要翻译：公开了一种使用可变退化电阻的自动增益可控线性差分放大器。线性差分放大器包括输入端，偏置电流源，负载单元，第一MOS晶体管和第二MOS晶体管。本发明的线性差分放大器可以根据输入信号控制放大增益，并提高线性度IIP3，而不需要通过提高线性度而引起的附加功耗。自动增益可控线性差分放大器使用NMOS / PMOS晶体管，因此可以更方便，高效地实现放大器的集成过程。

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