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1. 发明申请

US20120030639A1 COMPUTING DEVICE AND METHOD FOR CHECKING SIGNAL TRANSMISSION LINES 失效
标题翻译：用于检查信号传输线的计算装置和方法
公开(公告)号：US20120030639A1
公开(公告)日：2012-02-02
申请号：US12961908
申请日：2010-12-07
申请人： JIA-LU YE , SHI-PIAO LUO , CHIA-NAN PAI , SHOU-KUO HSU
发明人： JIA-LU YE , SHI-PIAO LUO , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/82
摘要： A computing device and a method selects a signal transmission line from a circuit board, computes an actual length of each line segment of the selected signal transmission line, and computes an actual distance between each line segment of the selected signal transmission line and a corresponding line segment of each neighboring signal transmission line. If each actual length is less than or equal to a corresponding reference length and each actual distance is more than or equal to a corresponding reference distance, the device and method determines a design of the selected signal transmission line satisfies the design standards. Otherwise, if any actual length is more than a corresponding reference length, or if any actual distance is less than a corresponding reference distance, the device and method determines the design of the signal transmission line does not satisfy the design standards.
摘要翻译：计算装置和方法从电路板选择信号传输线，计算所选择的信号传输线的每个线段的实际长度，并且计算所选信号传输线的每个线段与对应线之间的实际距离每个相邻信号传输线的段。如果每个实际长度小于或等于对应的参考长度，并且每个实际距离大于或等于相应的参考距离，则设备和方法确定所选信号传输线的设计满足设计标准。否则，如果任何实际长度大于相应的参考长度，或者如果任何实际距离小于相应的参考距离，则设备和方法确定信号传输线的设计不符合设计标准。

2. 发明申请

US20130097576A1 COMPUTING DEVICE AND METHOD FOR CHECKING VIA STUB 失效
标题翻译：计算机和通过STUB进行检查的方法
公开(公告)号：US20130097576A1
公开(公告)日：2013-04-18
申请号：US13327771
申请日：2011-12-16
申请人： JIA-LU YE , CHIA-NAN PAI , SHOU-KUO HSU
发明人： JIA-LU YE , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer-based method and a computing device for checking stub lengths of via stubs of a printed circuit board (PCB) layout are provided. The computing device displays a check interface, selects signal transmission line from a currently run PCB layout through the check interface, receives a reference stub length input through the check interface, and determines the actual stub length of each via stub of each via each selected signal transmission line connected to. The computing device further determines that a design of one via stub satisfies the design standards, if the actual stub length of the one stub via is less than or equal to the reference length, and determines that a design of one via stub does not satisfy the design standards if the actual stub length of the one via stub is greater than the reference stub length.
摘要翻译：提供了一种基于计算机的方法和用于检查印刷电路板（PCB）布局的通孔短截线的短截线长度的计算装置。计算装置显示检查接口，通过检查接口从当前运行的PCB布局中选择信号传输线，接收通过检查接口输入的参考短截线长度，并通过每个选定信号确定每个通孔短截线的实际短截线长度传输线连接。如果一个存根通孔的实际短截线长度小于或等于参考长度，则计算设备还确定一个通孔存根的设计满足设计标准，并且确定一个通孔存储体的设计不满足如果一个通过存根的实际存根长度大于参考短截线长度，则设计标准。

3. 发明申请

US20130254729A1 DEVICE AND METHOD FOR CHECKING SIGNAL TRANSMISSION LINES OF PCB LAYOUT FILES 审中-公开
标题翻译：检查PCB布局文件的信号传输线的装置和方法
公开(公告)号：US20130254729A1
公开(公告)日：2013-09-26
申请号：US13585855
申请日：2012-08-15
申请人： YA-LING HUANG , CHIA-NAN PAI , SHOU-KUO HSU
发明人： YA-LING HUANG , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/82
摘要： A device and a method reads a circuit printed circuit (PCB) layout file, extracts arrangement information of all the interference source components and signal transmission lines of the PCB layout file, and selects a interference source component from the PCB layout file, then determines if there is any signal transmission line is laid under the selected interference source component.
摘要翻译：一种设备和方法读取电路印刷电路（PCB）布局文件，提取PCB布局文件的所有干扰源组件和信号传输线的布置信息，并从PCB布局文件中选择干扰源组件，然后确定是否在所选择的干扰源组件下面有任何信号传输线。

4. 发明申请

US20130158925A1 COMPUTING DEVICE AND METHOD FOR CHECKING DIFFERENTIAL PAIR 审中-公开
标题翻译：计算设备和检查差异对的方法
公开(公告)号：US20130158925A1
公开(公告)日：2013-06-20
申请号：US13585856
申请日：2012-08-15
申请人： YA-LING HUANG , CHIA-NAN PAI , SHOU-KUO HSU
发明人： YA-LING HUANG , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： G06F19/00 , G01N37/00
CPC分类号： G06F17/5081
摘要： A computer-based method and a computing device for checking differential pairs of a printed circuit board layout are provided. The computing device determines the via pitch between switching vias of a differential pair according to the coordinates of the centers of the switching vias, determines the via gap between the switching vias of adjacent two differential pairs according to the radius and the coordinates of the centers of the switching vias, and determines that the switching vias does not satisfy design standards if the via pitch does not fall in an input via pitch range, or the via gap does not fall in an input via gap range.
摘要翻译：提供了一种用于检查印刷电路板布局的差分对的基于计算机的方法和计算装置。计算装置根据切换通孔的中心坐标来确定差分对的切换通孔之间的经过间距，根据半径的中心确定相邻两个差分对的切换通孔之间的通孔间隙并且如果通孔间距没有通过间距范围落入输入，或者通孔间隙不通过间隙范围落入输入，则确定开关通孔不满足设计标准。

5. 发明申请

US20120273254A1 SOLDERING PAD 有权
标题翻译：焊接垫
公开(公告)号：US20120273254A1
公开(公告)日：2012-11-01
申请号：US13217626
申请日：2011-08-25
申请人： HUA-LI ZHOU , CHIA-NAN PAI , SHOU-KUO HSU
发明人： HUA-LI ZHOU , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： H01B5/00
CPC分类号： H05K1/111 , H05K1/0242 , H05K1/025 , H05K2201/09736 , Y02P70/611
摘要： A pad includes a first mating section and a second mating section. The first mating section includes a first horizontal plane and a first inclined plane. The second mating section includes a second horizontal plane and a second inclined plane. The first mating section is a copper foil capable of being connected to a wire. The second mating section is made of insulating material. The first inclined plane and the second inclined plane are bonded together.
摘要翻译：垫包括第一配合部分和第二配合部分。第一配合部分包括第一水平面和第一倾斜平面。第二配合部分包括第二水平面和第二倾斜平面。第一配合部分是能够连接到电线的铜箔。第二配合部分由绝缘材料制成。第一倾斜平面和第二倾斜平面结合在一起。

6. 发明申请

US20120268283A1 CIRCUIT BOARD HAVING CURRENT BALANCE FUNCTION 审中-公开
标题翻译：具有当前平衡功能的电路板
公开(公告)号：US20120268283A1
公开(公告)日：2012-10-25
申请号：US13167719
申请日：2011-06-24
申请人： SHOU-KUO HSU , YUNG-CHIEH CHEN , HSIEN-CHUAN LIANG , SHEN-CHUN LI , WEN-LAING TSENG , CHIA-NAN PAI
发明人： SHOU-KUO HSU , YUNG-CHIEH CHEN , HSIEN-CHUAN LIANG , SHEN-CHUN LI , WEN-LAING TSENG , CHIA-NAN PAI
IPC分类号： G08B21/00 , G01R17/02
CPC分类号： H05K1/0201 , G01R31/043 , H05K1/0263 , H05K1/029 , H05K2201/0979 , H05K2201/10212
摘要： A circuit board includes a current balancing unit that receives a number of current values from ammeters. A minimum current value between the current values is determined by the current balancing unit. Resistance of one or more variable resistors of the current balancing unit is adjusted by the current balancing unit to make the current value from one or more the ammeters serially connected to the one or more the variable resistors to be substantially equal to the minimum current value.
摘要翻译：电路板包括从电流表接收多个电流值的电流平衡单元。当前值之间的最小电流值由电流平衡单元确定。通过电流平衡单元调整电流平衡单元的一个或多个可变电阻器的电阻，使来自一个或多个串联连接到一个或多个可变电阻器的电流器的电流值基本上等于最小电流值。

7. 发明申请

US20100277882A1 MOTHERBOARD AND MOTHERBOARD LAYOUT METHOD 有权
标题翻译：主板和母板布局方法
公开(公告)号：US20100277882A1
公开(公告)日：2010-11-04
申请号：US12503680
申请日：2009-07-15
申请人： CHIA-NAN PAI , HAN-LONG CHEN , NING LI , SHOU-KUO HSU
发明人： CHIA-NAN PAI , HAN-LONG CHEN , NING LI , SHOU-KUO HSU
IPC分类号： H05K1/18 , H05K3/30
CPC分类号： H05K1/0239 , H05K1/0245 , H05K1/0295 , H05K1/113 , H05K3/429 , H05K2201/044 , H05K2201/09254 , H05K2201/10015 , H05K2201/10545 , H05K2201/10636 , Y02P70/611 , Y10T29/4913
摘要： A motherboard layout method includes positioning two electronic elements on a top layer of a motherboard, and positioning another two electronic elements on a bottom layer of the motherboard, connecting one end of a first electronic element on the top layer to the same end of a first electronic element on the bottom layer with a first via hole, and connecting the same end of a second electronic element on the top layer to the same end of a second electronic element on the bottom layer with a second via hole. The method further includes connecting the other ends of the two electronic elements on the top layer to a first part, and connecting the other ends of the two electronic elements on the bottom layer to a second part.
摘要翻译：主板布局方法包括将两个电子元件定位在主板的顶层上，并且将另外两个电子元件定位在母板的底层上，将顶层上的第一电子元件的一端连接到第一电子元件的同一端电子元件在底层上具有第一通孔，并且通过第二通孔将顶层上的第二电子元件的同一端连接到底层上的第二电子元件的同一端。该方法还包括将顶层上的两个电子元件的另一端连接到第一部分，并将底层上的两个电子元件的另一端连接到第二部分。

8. 发明申请

US20110094783A1 PRINTED CIRCUIT BOARD 审中-公开
标题翻译：印刷电路板
公开(公告)号：US20110094783A1
公开(公告)日：2011-04-28
申请号：US12647396
申请日：2009-12-25
申请人： HUA-LI ZHOU , CHIA-NAN PAI , SHOU-KUO HSU
发明人： HUA-LI ZHOU , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： H05K1/16
CPC分类号： H05K1/0253 , H05K1/181 , H05K2201/09381 , H05K2201/0969 , H05K2201/10015 , H05K2201/10022 , H05K2201/10636 , Y02P70/611
摘要： A printed circuit board (PCB) includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path.
摘要翻译：印刷电路板（PCB）包括信号平面和参考平面。信号平面包括焊盘，安装在焊盘上的无源元件以及通过焊盘与无源元件电连接的信号传输线。参考平面为通过无源元件和传输线传输的信号提供返回路径。在对应于无源元件的参考平面中定义空隙，以增加返回路径的长度。

9. 发明申请

US20090260859A1 FLEXIBLE PRINTED CIRCUIT BOARD 审中-公开
标题翻译：柔性印刷电路板
公开(公告)号：US20090260859A1
公开(公告)日：2009-10-22
申请号：US12132067
申请日：2008-06-03
申请人： YU-CHANG PAI , SHOU-KUO HSU , CHIA-NAN PAI
发明人： YU-CHANG PAI , SHOU-KUO HSU , CHIA-NAN PAI
IPC分类号： H05K1/02 , H05K3/10
CPC分类号： H05K1/0245 , H05K1/0224 , H05K1/0253 , H05K1/0393 , H05K2201/09236 , H05K2201/09318 , H05K2201/0969 , Y10T29/49155
摘要： A flexible printed circuit board (FPCB) includes a signal layer comprising a differential pair, a ground layer comprising a grounded sheet made of conductive material, and a dielectric layer located between the signal layer and the ground layer. A void is located on the two opposite sides of the grounded sheet in the ground layer. The differential pair comprises two transmission lines and each transmission line is capable of transmitting a differential signal. The distances between the middle line of the grounded sheet and the middle line of each of the two transmission lines are equal.
摘要翻译：柔性印刷电路板（FPCB）包括包含差分对的信号层，包括由导电材料制成的接地片的接地层和位于信号层和接地层之间的电介质层。在接地层的接地片的两个相对侧上设有空隙。差分对包括两条传输线，每条传输线都能传输一个差分信号。接地片材的中间线与两条传输线路中间线的距离相等。

10. 发明申请

US20130049461A1 CIRCUIT TOPOLOGY OF PRINTED CIRCUIT BOARD 审中-公开
标题翻译：印刷电路板电路拓扑
公开(公告)号：US20130049461A1
公开(公告)日：2013-02-28
申请号：US13336000
申请日：2011-12-23
申请人： SHI-PIAO LUO , HUA-LI ZHOU , CHIA-NAN PAI , SHOU-KUO HSU
发明人： SHI-PIAO LUO , HUA-LI ZHOU , CHIA-NAN PAI , SHOU-KUO HSU
IPC分类号： H02J4/00
CPC分类号： H05K1/0248 , H03K5/1534 , H03K19/00346 , H04L25/0278 , H05K1/0231 , H05K1/0246 , H05K2201/10015 , Y10T307/25
摘要： A circuit topology for multiple loads includes a driving terminal, first and second signal receiving terminals, and a capacitor. The driving terminal is connected to a node through a first transmission line. The node is connected to the first and second signal receiving terminals through second and third transmission lines. The second transmission line is longer than the third transmission line, and a difference between lengths of the second and third transmission lines is greater than a product of a transmission speed and a rise time of signals from the driving terminal. A first terminal of the capacitor is connected to the third transmission line. A second terminal of the capacitor is grounded. A distance between the capacitor and the second signal receiving terminal is less than a distance between the capacitor and the node.
摘要翻译：用于多个负载的电路拓扑包括驱动端子，第一和第二信号接收端子以及电容器。驱动终端通过第一传输线连接到节点。节点通过第二和第三传输线连接到第一和第二信号接收终端。第二传输线比第三传输线长，并且第二传输线和第三传输线的长度之间的差大于来自驱动终端的信号的传输速度和上升时间的乘积。电容器的第一端子连接到第三传输线。电容器的第二个端子接地。电容器和第二信号接收端子之间的距离小于电容器和节点之间的距离。

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