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1. 发明申请

US20120204012A1 CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM 有权
标题翻译：基于数据处理系统中的错误检测模式的可配置管道
公开(公告)号：US20120204012A1
公开(公告)日：2012-08-09
申请号：US13446930
申请日：2012-04-13
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/30 , G06F9/302 , G06F9/305 , G06F9/312
CPC分类号： G06F9/3875 , G06F9/3004 , G06F9/30181 , G06F9/30189 , G06F9/38 , G06F9/3861 , G06F9/3867 , G06F11/1004 , G06F11/1008 , G06F11/1076
摘要： A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
摘要翻译：一种方法包括提供具有指令流水线的数据处理器，其中指令流水线具有多个指令流水线级，并且其中多条指令流水线级包括第一指令流水线级和第二指令流水线级。该方法还包括提供数据处理器指令，使数据处理器在数据处理器指令的执行期间执行第一组计算操作，如果数据处理器指令正在执行，则在第一指令流水线阶段执行第一组计算操作执行并且已经选择了第一模式，并且如果正在执行数据处理器指令并且已经选择了第二模式，则在第二指令流水线级中执行第一组计算操作。

2. 发明授权

US07937573B2 Metric for selective branch target buffer (BTB) allocation 有权
标题翻译：用于选择性分支目标缓冲区（BTB）分配的度量标准
公开(公告)号：US07937573B2
公开(公告)日：2011-05-03
申请号：US12040210
申请日：2008-02-29
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/32 , G06F9/34
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3804 , G06F9/382
摘要： A method and data processing system allocates entries in a branch target buffer (BTB). Instructions are fetched from a plurality of instructions and one of the plurality of instructions is determined to be a branch instruction. A corresponding branch target address is determined. A determination is made whether the branch target address is stored in a branch target buffer (BTB). When the branch target address is not stored in the branch target buffer, an entry in the branch target buffer is identified for allocation to receive the branch target address based upon stored metrics such as data processing cycle saving information and branch prediction state. In one form the stored metrics are stored in predetermined fields of the entries of the BTB.
摘要翻译：方法和数据处理系统在分支目标缓冲器（BTB）中分配条目。指令从多个指令中取出，并且多个指令中的一个被确定为分支指令。确定相应的分支目标地址。确定分支目标地址是否存储在分支目标缓冲器（BTB）中。当分支目标地址未被存储在分支目标缓冲器中时，识别分支目标缓冲器中的条目用于分配以基于存储的诸如数据处理周期保存信息和分支预测状态的指标来接收分支目标地址。在一种形式中，存储的度量被存储在BTB的条目的预定字段中。

3. 发明授权

US07895422B2 Selective postponement of branch target buffer (BTB) allocation 有权
标题翻译：分支目标缓冲区（BTB）分配的选择性推迟
公开(公告)号：US07895422B2
公开(公告)日：2011-02-22
申请号：US12040204
申请日：2008-02-29
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/38 , G06F9/44
CPC分类号： G06F9/3806 , G06F9/3802 , G06F9/3814 , G06F9/3844
摘要： A system and method provides branch target buffer (BTB) allocation. When a branch instruction is received, a branch target address that corresponds to the branch instruction is determined. A determination is made whether the branch target address is presently stored in a branch target buffer (BTB). When the branch target address is not presently stored in the branch target buffer, an entry in the branch target buffer is identified to receive the branch target address. A value in a field within the identified entry in the branch target buffer, such as a postponement flag (PF), is used to selectively override a replacement decision defined by predetermined branch target buffer allocation criteria. In one form, if a branch is taken, the identified entry is replaced with the branch target address in response to determining that the value in the field within the identified entry has a predetermined value.
摘要翻译：系统和方法提供分支目标缓冲区（BTB）分配。当接收到分支指令时，确定与分支指令对应的分支目标地址。确定分支目标地址是否当前存储在分支目标缓冲器（BTB）中。当分支目标地址当前不存储在分支目标缓冲器中时，识别分支目标缓冲器中的条目以接收分支目标地址。使用分支目标缓冲器中的所识别的条目中的字段中的值（诸如推迟标志（PF））来选择性地覆盖由预定分支目标缓冲器分配标准定义的替换决策。在一种形式中，如果采取分支，则响应于确定所识别的条目中的字段中的值具有预定值，将所标识的条目替换为分支目标地址。

4. 发明授权

US06751724B1 Method and apparatus for instruction fetching 失效
标题翻译：指令取出方法和装置
公开(公告)号：US06751724B1
公开(公告)日：2004-06-15
申请号：US09552118
申请日：2000-04-19
申请人： William C. Moyer , Jeffrey W. Scott , James S. Thomas , John H. Arends , John J. Vaglica
发明人： William C. Moyer , Jeffrey W. Scott , James S. Thomas , John H. Arends , John J. Vaglica
IPC分类号： G06F930
CPC分类号： G06F9/3814 , G06F9/3802
摘要： Embodiments of the present invention relate to instruction fetching in data processing systems. One aspect involves a data processor (202) to execute instructions and to fetch instructions from a memory (208) according to a fetch size. This data processor (202) comprises a first input (212) to receive instructions, control logic (402) to decode the instructions, and an instruction pipeline (400) coupled to the first input (212) and the control logic (400). The instruction pipeline (400) is responsive to a first signal (214) to set the fetch size to one of a first size and a second size. The data processor (202) therefore allows an instruction fetch policy to be altered based on the characteristics of an accessed device in order to achieve improved performance.
摘要翻译：本发明的实施例涉及在数据处理系统中的指令取出。一个方面涉及一种数据处理器（202），用于执行指令并根据取出大小从存储器（208）获取指令。该数据处理器（202）包括用于接收指令的第一输入（212），解码指令的控制逻辑（402）以及耦合到第一输入（212）和控制逻辑（400）的指令流水线（400）。指令流水线（400）响应于第一信号（214）将获取大小设置为第一大小和第二大小中的一个。因此，数据处理器（202）允许基于所访问设备的特性来改变指令获取策略，以便实现改进的性能。

5. 发明授权

US06401196B1 Data processor system having branch control and method thereof 失效
标题翻译：具有分支控制的数据处理器系统及其方法
公开(公告)号：US06401196B1
公开(公告)日：2002-06-04
申请号：US09100669
申请日：1998-06-19
申请人： Lea Hwang Lee , William C. Moyer , Jeffrey W. Scott , John H. Arends
发明人： Lea Hwang Lee , William C. Moyer , Jeffrey W. Scott , John H. Arends
IPC分类号： G06F912
CPC分类号： G06F9/324 , G06F9/325
摘要： A specific implementation is disclosed where a backward branch address instruction is fetched at a branch address. The backward branch instruction has an offset value to define the size of a program loop. A counter is set to a value that is proportional to the size of the loop. In one example the counter is set to the offset value. As each instruction of the loop is executed the counter is modified to indicate a remaining number of instructions in the loop. When no instructions remain in the current pass of the loop, the counter is reset to the offset value and the loop is repeated until a termination condition encountered. As part of the implementation the instruction after the branch instruction is read and stored prior to the loop being executed.
摘要翻译：公开了在分支地址处取出反向分支地址指令的具体实现。后向分支指令具有一个偏移值，用于定义程序循环的大小。计数器设置为与循环大小成比例的值。在一个示例中，计数器设置为偏移值。当执行循环的每个指令时，计数器被修改以指示循环中剩余的指令数。当循环当前通过中没有指令时，计数器将重置为偏移值，并重复循环直到遇到终止条件。作为实现的一部分，在循环执行之前读取并存储分支指令之后的指令。

6. 发明授权

US5983338A Method and apparatus for interfacing a processor to a coprocessor for communicating register write information 失效
标题翻译：用于将处理器连接到协处理器以用于传送寄存器写入信息的方法和装置
公开(公告)号：US5983338A
公开(公告)日：1999-11-09
申请号：US924508
申请日：1997-09-05
申请人： William C. Moyer , John Arends , Jeffrey W. Scott
发明人： William C. Moyer , John Arends , Jeffrey W. Scott
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/4217
摘要： A processor to coprocessor interface supporting multiple coprocessors utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor and coprocessor on a bidirectional shared bus either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.
摘要翻译：支持多个协处理器的协处理器接口的处理器利用编译器可生成的软件类型函数调用和返回，指令执行以及可变负载和存储接口指令。数据在双向共享总线上的处理器和协处理器之间移动，隐式地通过寄存器侦听和广播，或通过函数调用和返回以及可变加载和存储接口指令明确地移动。加载和存储接口指令允许选择性存储器地址预增量。双向总线可以在每个时钟周期两方面驱动。接口分离接口指令解码和执行。通过在执行信号被断言之前否定解码信号来指示解码的指令丢弃来提供流水线操作。

7. 发明授权

US09448942B2 Random access of a cache portion using an access module 有权
标题翻译：使用访问模块随机访问缓存部分
公开(公告)号：US09448942B2
公开(公告)日：2016-09-20
申请号：US13690888
申请日：2012-11-30
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F12/08 , G11C7/24 , G11C5/14 , G11C29/12
CPC分类号： G06F12/0864 , G06F12/0802 , G11C5/14 , G11C7/24 , G11C29/12 , Y02D10/13
摘要： A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.
摘要翻译：一种具有第一处理器，第二处理器，第二处理器的本地存储器和第二处理器的内置自检（BIST）控制器的数据处理系统，其可以被随机地启用以对本地存储器执行存储器访问的第二处理器，并且包括随机值发生器。该系统可以执行包括由第一处理器执行安全代码序列并且由第二处理器的BIST控制器响应于随机值生成器对第二处理器的本地存储器进行BIST存储器访问的方法。执行BIST存储器访问同时执行安全代码序列。

8. 发明申请

US20130246750A1 CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM 审中-公开
公开(公告)号：US20130246750A1
公开(公告)日：2013-09-19
申请号：US13750345
申请日：2013-01-25
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/38
CPC分类号： G06F9/3875 , G06F9/3004 , G06F9/30181 , G06F9/30189 , G06F9/38 , G06F9/3861 , G06F9/3867 , G06F11/1004 , G06F11/1008 , G06F11/1076
摘要： A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

9. 发明授权

US08190860B2 Result forwarding to dependent instruction in pipelined processor with mode selectable execution in E1 or E2 of pipelined operational stages 有权
标题翻译：在流水线操作阶段的E1或E2中，可以在流水线处理器中转换为依赖指令
公开(公告)号：US08190860B2
公开(公告)日：2012-05-29
申请号：US12872771
申请日：2010-08-31
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/38
CPC分类号： G06F9/3875 , G06F9/3004 , G06F9/30181 , G06F9/30189 , G06F9/38 , G06F9/3861 , G06F9/3867 , G06F11/1004 , G06F11/1008 , G06F11/1076
摘要： A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
摘要翻译：一种方法包括提供具有指令流水线的数据处理器，其中指令流水线具有多个指令流水线级，并且其中多条指令流水线级包括第一指令流水线级和第二指令流水线级。该方法还包括提供数据处理器指令，使数据处理器在数据处理器指令的执行期间执行第一组计算操作，如果数据处理器指令正在执行，则在第一指令流水线阶段执行第一组计算操作执行并且已经选择了第一模式，并且如果正在执行数据处理器指令并且已经选择了第二模式，则在第二指令流水线级中执行第一组计算操作。

10. 发明申请

US20100332940A1 CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM 有权
标题翻译：基于数据处理系统中的错误检测模式的可配置管道
公开(公告)号：US20100332940A1
公开(公告)日：2010-12-30
申请号：US12872771
申请日：2010-08-31
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/38 , H03M13/05 , G06F11/10
CPC分类号： G06F9/3875 , G06F9/3004 , G06F9/30181 , G06F9/30189 , G06F9/38 , G06F9/3861 , G06F9/3867 , G06F11/1004 , G06F11/1008 , G06F11/1076
摘要： A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
摘要翻译：一种方法包括提供具有指令流水线的数据处理器，其中指令流水线具有多个指令流水线级，并且其中多条指令流水线级包括第一指令流水线级和第二指令流水线级。该方法还包括提供数据处理器指令，使数据处理器在数据处理器指令的执行期间执行第一组计算操作，如果数据处理器指令正在执行，则在第一指令流水线阶段执行第一组计算操作执行并且已经选择了第一模式，并且如果正在执行数据处理器指令并且已经选择了第二模式，则在第二指令流水线级中执行第一组计算操作。

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