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1. 发明授权

US06327647B1 Method and apparatus for interfacing a processor to a coprocessor 有权
标题翻译：将处理器与协处理器进行接口的方法和装置
公开(公告)号：US06327647B1
公开(公告)日：2001-12-04
申请号：US09609260
申请日：2000-06-30
申请人： William C. Moyer , John Arends , Jeffrey W. Scott
发明人： William C. Moyer , John Arends , Jeffrey W. Scott
IPC分类号： G06F1500
CPC分类号： G06F9/3012 , G06F9/30116 , G06F9/3861 , G06F9/3879 , G06F9/3881
摘要： A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.
摘要翻译：支持多个协处理器（14,16）的协处理器（14）接口的处理器（12）利用编译器可产生的软件类型函数调用和返回，指令执行以及可变加载和存储接口指令。数据在双向共享总线（28）上的处理器（12）和协处理器（14）之间隐含地通过寄存器窥探和广播来移动，或通过功能调用和返回以及可变负载和存储接口指令明确地移动。加载和存储接口指令允许选择性存储器地址预增量。双向总线（28）可以在每个时钟周期两方面潜在地驱动。接口分离接口指令解码和执行。通过在执行信号被断言之前否定解码信号来指示解码的指令丢弃来提供流水线操作。

2. 发明授权

US07007154B2 Method and apparatus for interfacing a processor to a coprocessor 有权
公开(公告)号：US07007154B2
公开(公告)日：2006-02-28
申请号：US10007836
申请日：2001-11-05
申请人： William C. Moyer , John Arends , Jeffrey W. Scott
发明人： William C. Moyer , John Arends , Jeffrey W. Scott
IPC分类号： G06F15/00
CPC分类号： G06F9/3012 , G06F9/30116 , G06F9/3861 , G06F9/3879 , G06F9/3881
摘要： A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

3. 发明授权

US06505290B1 Method and apparatus for interfacing a processor to a coprocessor 失效
公开(公告)号：US06505290B1
公开(公告)日：2003-01-07
申请号：US08924518
申请日：1997-09-05
申请人： William C. Moyer , John Arends , Jeffrey W. Scott
发明人： William C. Moyer , John Arends , Jeffrey W. Scott
IPC分类号： G06F1500
CPC分类号： G06F9/3012 , G06F9/30116 , G06F9/3861 , G06F9/3879 , G06F9/3881
摘要： A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

4. 发明授权

US5983338A Method and apparatus for interfacing a processor to a coprocessor for communicating register write information 失效
标题翻译：用于将处理器连接到协处理器以用于传送寄存器写入信息的方法和装置
公开(公告)号：US5983338A
公开(公告)日：1999-11-09
申请号：US924508
申请日：1997-09-05
申请人： William C. Moyer , John Arends , Jeffrey W. Scott
发明人： William C. Moyer , John Arends , Jeffrey W. Scott
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/4217
摘要： A processor to coprocessor interface supporting multiple coprocessors utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor and coprocessor on a bidirectional shared bus either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.
摘要翻译：支持多个协处理器的协处理器接口的处理器利用编译器可生成的软件类型函数调用和返回，指令执行以及可变负载和存储接口指令。数据在双向共享总线上的处理器和协处理器之间移动，隐式地通过寄存器侦听和广播，或通过函数调用和返回以及可变加载和存储接口指令明确地移动。加载和存储接口指令允许选择性存储器地址预增量。双向总线可以在每个时钟周期两方面驱动。接口分离接口指令解码和执行。通过在执行信号被断言之前否定解码信号来指示解码的指令丢弃来提供流水线操作。

5. 发明授权

US5923893A Method and apparatus for interfacing a processor to a coprocessor 失效
公开(公告)号：US5923893A
公开(公告)日：1999-07-13
申请号：US924137
申请日：1997-09-05
申请人： William C. Moyer , John Arends , Jeffrey W. Scott
发明人： William C. Moyer , John Arends , Jeffrey W. Scott
IPC分类号： G06F9/30 , G06F9/38 , G06F15/76
CPC分类号： G06F9/3012 , G06F9/3861 , G06F9/3879 , G06F9/3881
摘要： A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

6. 发明授权

US10007522B2 System and method for selectively allocating entries at a branch target buffer 有权
公开(公告)号：US10007522B2
公开(公告)日：2018-06-26
申请号：US14282290
申请日：2014-05-20
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F9/32 , G06F9/42 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/3808 , G06F9/3844
摘要： A branch instruction and a corresponding branch instruction address are received at a data processing system. A first value is received and is compared to a portion of the branch instruction address. An entry at a branch target buffer corresponding to the branch instruction is selectively allocated based on a result of the comparing.

7. 发明授权

US09311099B2 Systems and methods for locking branch target buffer entries 有权
标题翻译：用于锁定分支目标缓冲区条目的系统和方法
公开(公告)号：US09311099B2
公开(公告)日：2016-04-12
申请号：US13955106
申请日：2013-07-31
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F9/22 , G06F9/38
CPC分类号： G06F9/3806
摘要： A data processing system includes a processor configured to execute processor instructions and a branch target buffer having a plurality of entries. Each entry is configured to store a branch target address and a lock indicator, wherein the lock indicator indicates whether the entry is a candidate for replacement, and wherein the processor is configured to access the branch target buffer during execution of the processor instructions. The data processing system further includes control circuitry configured to determine a fullness level of the branch target buffer, wherein in response to the fullness level reaching a fullness threshold, the control circuitry is configured to assert the lock indicator of one or more of the plurality of entries to indicate that the one or more of the plurality of entries is not a candidate for replacement.
摘要翻译：数据处理系统包括被配置为执行处理器指令的处理器和具有多个条目的分支目标缓冲器。每个条目被配置为存储分支目标地址和锁定指示符，其中所述锁定指示符指示所述条目是否是替换的候选，并且其中所述处理器被配置为在所述处理器指令的执行期间访问所述分支目标缓冲器。数据处理系统还包括配置成确定分支目标缓冲器的饱和度水平的控制电路，其中响应于饱和度达到饱和阈值，控制电路被配置为断言多个条目，以指示所述多个条目中的一个或多个条目不是替换候选者。

8. 发明申请

US20150339124A1 SYSTEM AND METHOD FOR SELECTIVELY ALLOCATING ENTRIES AT A BRANCH TARGET BUFFER 有权
标题翻译：在分支目标缓存器中选择分配入口的系统和方法
公开(公告)号：US20150339124A1
公开(公告)日：2015-11-26
申请号：US14282290
申请日：2014-05-20
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/3808 , G06F9/3844
摘要： A branch instruction and a corresponding branch instruction address are received at a data processing system. A first value is received and is compared to a portion of the branch instruction address. An entry at a branch target buffer corresponding to the branch instruction is selectively allocated based on a result of the comparing.
摘要翻译：在数据处理系统处接收分支指令和对应的分支指令地址。接收到第一个值，并将其与分支指令地址的一部分进行比较。基于比较的结果，选择性地分配与分支指令对应的分支目标缓冲器中的条目。

9. 发明申请

US20150039945A1 DATA PROCESSOR DEVICE FOR HANDLING A WATCHPOINT AND METHOD THEREOF 有权
标题翻译：用于处理观察点的数据处理器装置及其方法
公开(公告)号：US20150039945A1
公开(公告)日：2015-02-05
申请号：US13955102
申请日：2013-07-31
申请人： WILLIAM C. MOYER , Jeffrey W. Scott
发明人： WILLIAM C. MOYER , Jeffrey W. Scott
IPC分类号： G06F11/34
CPC分类号： G06F11/36 , G06F11/3072 , G06F11/3082 , G06F11/3636
摘要： Upon detecting an occurrence of a watchpoint event for debugging a computer processing system, at least a portion of at least one message in a trace message buffer is flushed when a characteristic of the at least one of the messages matches a specified characteristic.
摘要翻译：当检测到用于调试计算机处理系统的观察点事件的发生时，当所述至少一个消息的特性与指定的特性匹配时，跟踪消息缓冲器中的至少一个消息的至少一部分被刷新。

10. 发明申请

US20140068346A1 DATA PROCESSOR DEVICE FOR HANDLING A WATCHPOINT AND METHOD THEREOF 有权
标题翻译：用于处理观察点的数据处理器装置及其方法
公开(公告)号：US20140068346A1
公开(公告)日：2014-03-06
申请号：US13598240
申请日：2012-08-29
申请人： Jeffrey W. Scott , William C. Moyer
发明人： Jeffrey W. Scott , William C. Moyer
IPC分类号： G06F11/34
CPC分类号： G06F11/3636
摘要： During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being flushed from the trace FIFO before the trace information has been communicated to a trace analyzer.
摘要翻译：在数据处理器的调试操作模式期间，在数据处理器确定观察点事件已经发生，并且作为响应，存储跟尚未传送到调试器的跟踪信息的跟踪FIFO的操作条件被改变。例如，FIFO追查观察点的发生导致跟踪信息在跟踪信息已被传送到跟踪分析器之前被从跟踪FIFO刷新。

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