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1. 发明授权

US07757109B2 Circuit arrangement for activating a circuit block and method for the same 有权
标题翻译：用于激活电路块的电路布置及其方法
公开(公告)号：US07757109B2
公开(公告)日：2010-07-13
申请号：US11454302
申请日：2006-06-15
申请人： Jörg Berthold , Georg Georgakos , Stephan Henzler , Thomas Nirschl , Matthias Schobinger , Doris Schmitt-Landsiedel
发明人： Jörg Berthold , Georg Georgakos , Stephan Henzler , Thomas Nirschl , Matthias Schobinger , Doris Schmitt-Landsiedel
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit includes functional blocks, a power control unit controlling the provision of power to the different functional blocks of the integrated circuit, a detecting unit detecting if a turned off functional block is to be turned on, and a clock signal control unit controlling the provision of the clock signal for the functional blocks. The clock signal control unit interrupts the clock signal for the activated functional blocks of the integrated circuit for a predetermined number of clock cycles. The power control unit provides power to the turned off functional block during the interrupted clock cycles.
摘要翻译：集成电路包括功能块，控制向集成电路的不同功能块提供电力的功率控制单元，检测关闭功能块是否被接通的检测单元，以及控制该功能块的时钟信号控制单元提供功能块的时钟信号。时钟信号控制单元在预定数量的时钟周期中断集成电路的激活功能块的时钟信号。电源控制单元在中断的时钟周期期间向关闭的功能块供电。

2. 发明授权

US07427882B2 Method and apparatus for switching on a voltage supply of a semiconductor circuit and corresponding semiconductor circuit 有权
标题翻译：用于接通半导体电路和对应的半导体电路的电压源的方法和装置
公开(公告)号：US07427882B2
公开(公告)日：2008-09-23
申请号：US11498505
申请日：2006-08-03
申请人： Stephan Henzler , Jörg Berthold , Christian Pacha , Doris Schmitt-Landsiedel , Thomas Nirschl , Georg Georgakos
发明人： Stephan Henzler , Jörg Berthold , Christian Pacha , Doris Schmitt-Landsiedel , Thomas Nirschl , Georg Georgakos
IPC分类号： H03L7/00
CPC分类号： H03K17/567 , H03K17/163 , H03K17/687
摘要： A method and an apparatus for switching on a voltage supply of a voltage domain of a semiconductor circuit is disclosed. A voltage supply is connected to a supply voltage of the semiconductor circuit by means of a switchable element. The switchable element is activated in such a way that, for switching on the voltage supply of the voltage domain, a current through the switchable element rises progressively with at least one intermediate value, in particular stepwise manner.
摘要翻译：公开了一种用于接通半导体电路的电压域的电压源的方法和装置。电压源通过可切换元件连接到半导体电路的电源电压。可切换元件被激活，使得为了接通电压域的电压源，通过可切换元件的电流以至少一个中间值，特别是逐步的方式逐渐升高。

3. 发明授权

US07411423B2 Logic activation circuit 有权
标题翻译：逻辑启动电路
公开(公告)号：US07411423B2
公开(公告)日：2008-08-12
申请号：US11194495
申请日：2005-08-01
申请人： Jörg Berthold , Georg Georgakos , Stephan Henzler , Doris Schmitt-Landsiedel
发明人： Jörg Berthold , Georg Georgakos , Stephan Henzler , Doris Schmitt-Landsiedel
IPC分类号： H03K19/096
CPC分类号： H03K19/0016
摘要： Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of the logic circuit in a manner dependent on a changeover control signal that is applied to a control terminal of the voltage supply switching device; and having (b) a charge equalization switching device which, in a manner dependent on a control switching pulse, connects the supply voltage line of the logic circuit to the control terminal of the voltage supply switching device for the duration of the control switching pulse so that charge equalization is effected between the supply voltage line and the control terminal of the voltage supply switching device in order to generate the changeover control signal.
摘要翻译：逻辑启动电路，用于切换具有至少一个电源电压线的逻辑电路，所述逻辑启动电路具有：（a）至少一个电压供应切换装置，用于将电源电压连接到逻辑电路的电源电压线取决于施加到电压切换装置的控制端的切换控制信号的方式; 并且具有（b）电荷均衡切换装置，其以取决于控制切换脉冲的方式，在控制切换脉冲的持续时间内将逻辑电路的电源电压线连接到电源开关装置的控制端子在电源电压线和电源切换装置的控制端之间进行充电均衡，以产生转换控制信号。

4. 发明申请

US20070038876A1 Circuit arrangement for activating a circuit block and method for the same 有权
标题翻译：用于激活电路块的电路布置及其方法
公开(公告)号：US20070038876A1
公开(公告)日：2007-02-15
申请号：US11454302
申请日：2006-06-15
申请人： Jorg Berthold , Geor Georgakos , Stephan Henzler , Thomas Nirschl , Matthias Schobinger , Doris Schmitt-Landsiedel
发明人： Jorg Berthold , Geor Georgakos , Stephan Henzler , Thomas Nirschl , Matthias Schobinger , Doris Schmitt-Landsiedel
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit includes functional blocks, a power control unit controlling the provision of power to the different functional blocks of the integrated circuit, a detecting unit detecting if a turned off functional block is to be turned on, and a clock signal control unit controlling the provision of the clock signal for the functional blocks. The clock signal control unit interrupts the clock signal for the activated functional blocks of the integrated circuit for a predetermined number of clock cycles. The power control unit provides power to the turned off functional block during the interrupted clock cycles.
摘要翻译：集成电路包括功能块，控制向集成电路的不同功能块提供电力的功率控制单元，检测关闭功能块是否被接通的检测单元，以及控制该功能块的时钟信号控制单元提供功能块的时钟信号。时钟信号控制单元在预定数量的时钟周期中断集成电路的激活功能块的时钟信号。电源控制单元在中断的时钟周期期间向关闭的功能块供电。

5. 发明申请

US20070085573A1 Method and apparatus for switching on a voltage supply of a semiconductor circuit and corresponding semiconductor circuit 有权
标题翻译：用于接通半导体电路和对应的半导体电路的电压源的方法和装置
公开(公告)号：US20070085573A1
公开(公告)日：2007-04-19
申请号：US11498505
申请日：2006-08-03
申请人： Stephan Henzler , Jorg Berthold , Christian Pacha , Doris Schmitt-Landsiedel , Thomas Nirschl , Georg Georgakos
发明人： Stephan Henzler , Jorg Berthold , Christian Pacha , Doris Schmitt-Landsiedel , Thomas Nirschl , Georg Georgakos
IPC分类号： H03L7/00
CPC分类号： H03K17/567 , H03K17/163 , H03K17/687
摘要： A method and an apparatus for switching on a voltage supply of a voltage domain of a semiconductor circuit is disclosed. A voltage supply is connected to a supply voltage of the semiconductor circuit by means of a switchable element. The switchable element is activated in such a way that, for switching on the voltage supply of the voltage domain, a current through the switchable element rises progressively with at least one intermediate value, in particular stepwise manner.
摘要翻译：公开了一种用于接通半导体电路的电压域的电压源的方法和装置。电压源通过可切换元件连接到半导体电路的电源电压。可切换元件被激活，使得为了接通电压域的电压源，通过可切换元件的电流以至少一个中间值，特别是逐步的方式逐渐升高。

6. 发明授权

US07471580B2 Flip-flop with additional state storage in the event of turn-off 有权
标题翻译：在关闭的情况下，触发器附加状态存储
公开(公告)号：US07471580B2
公开(公告)日：2008-12-30
申请号：US11274048
申请日：2005-11-15
申请人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
发明人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
IPC分类号： G11C7/02
CPC分类号： G11C11/412
摘要： The flip-flop according to the invention serves for storing an item of logic state information and has at least one data input and at least one data output. The flip-flop comprises at least one latch stage for storing the state information if the flip-flop is switched on. Furthermore, the flip-flop according to the invention comprises at least one memory cell having a capacitance as storage element. In this case, the at least one memory cell serves for storing the state information if the flip-flop is switched off.
摘要翻译：根据本发明的触发器用于存储一个逻辑状态信息项，并具有至少一个数据输入和至少一个数据输出。如果触发器被接通，触发器包括用于存储状态信息的至少一个锁存级。此外，根据本发明的触发器包括具有作为存储元件的电容的至少一个存储单元。在这种情况下，如果触发器被关闭，则至少一个存储单元用于存储状态信息。

7. 发明申请

US20060119406A1 Flip-flop with additional state storage in the event of turn-off 有权
标题翻译：在关闭的情况下，触发器附加状态存储
公开(公告)号：US20060119406A1
公开(公告)日：2006-06-08
申请号：US11274048
申请日：2005-11-15
申请人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
发明人： Stephan Henzler , Joerg Berthold , Georg Georgakos , Doris Schmitt-Landsiedel , Christian Pacha
IPC分类号： H03K3/356
CPC分类号： G11C11/412
摘要： The flip-flop according to the invention serves for storing an item of logic state information and has at least one data input and at least one data output. The flip-flop comprises at least one latch stage for storing the state information if the flip-flop is switched on. Furthermore, the flip-flop according to the invention comprises at least one memory cell having a capacitance as storage element. In this case, the at least one memory cell serves for storing the state information if the flip-flop is switched off.
摘要翻译：根据本发明的触发器用于存储一个逻辑状态信息项，并具有至少一个数据输入和至少一个数据输出。如果触发器被接通，触发器包括用于存储状态信息的至少一个锁存级。此外，根据本发明的触发器包括具有作为存储元件的电容的至少一个存储单元。在这种情况下，如果触发器被关闭，则至少一个存储单元用于存储状态信息。

8. 发明申请

US20060022712A1 Logic activation circuit 有权
标题翻译：逻辑启动电路
公开(公告)号：US20060022712A1
公开(公告)日：2006-02-02
申请号：US11194495
申请日：2005-08-01
申请人： Jorg Berthold , Georg Georgakos , Stephan Henzler , Doris Schmitt-Landsiedel
发明人： Jorg Berthold , Georg Georgakos , Stephan Henzler , Doris Schmitt-Landsiedel
IPC分类号： H03K19/094
CPC分类号： H03K19/0016
摘要： Logic activation circuit for switching a logic circuit having at least one supply voltage line on or off, said logic activation circuit having: (a) at least one voltage supply switching device for connecting a supply voltage to a supply voltage line of the logic circuit in a manner dependent on a changeover control signal that is applied to a control terminal of the voltage supply switching device; and having (b) a charge equalization switching device which, in a manner dependent on a control switching pulse, connects the supply voltage line of the logic circuit to the control terminal of the voltage supply switching device for the duration of the control switching pulse so that charge equalization is effected between the supply voltage line and the control terminal of the voltage supply switching device in order to generate the changeover control signal.
摘要翻译：逻辑启动电路，用于切换具有至少一个电源电压线的逻辑电路，所述逻辑启动电路具有：（a）至少一个电压供应切换装置，用于将电源电压连接到逻辑电路的电源电压线取决于施加到电压切换装置的控制端的切换控制信号的方式; 并且具有（b）电荷均衡切换装置，其以取决于控制切换脉冲的方式，在控制切换脉冲的持续时间内将逻辑电路的电源电压线连接到电源开关装置的控制端子在电源电压线和电源切换装置的控制端之间进行充电均衡，以产生转换控制信号。

9. 发明申请

US20090115468A1 Integrated Circuit and Method for Operating an Integrated Circuit 审中-公开
标题翻译：集成电路和操作集成电路的方法
公开(公告)号：US20090115468A1
公开(公告)日：2009-05-07
申请号：US12090165
申请日：2006-09-28
申请人： Joerg Berthold , Matthias Eireiner , Georg Georgakos , Stephan Henzler , Christian Pacha , Doris Schmitt-Landsiedel
发明人： Joerg Berthold , Matthias Eireiner , Georg Georgakos , Stephan Henzler , Christian Pacha , Doris Schmitt-Landsiedel
IPC分类号： H03L7/00
CPC分类号： H03K3/356156
摘要： An integrated circuit, comprising a first data retention element configured to retain the data, the first data retention element having a first setup time, and a second data retention element configured to retain the data, the second data retention element having a second setup time, the second data retention element further having a data input. The second data retention element is connected in parallel with the first data retention element, and the second data retention element is configurable via the data input such that the second setup time is longer than the first setup time.
摘要翻译：一种集成电路，包括被配置为保留数据的第一数据保持元件，具有第一建立时间的第一数据保持元件和被配置为保留数据的第二数据保持元件，第二数据保持元件具有第二建立时间，所述第二数据保留元件还具有数据输入。第二数据保持元件与第一数据保持元件并联连接，并且第二数据保持元件可经由数据输入配置，使得第二建立时间比第一建立时间长。

10. 发明申请

US20060273838A1 Master latch circuit with signal level displacement for a dynamic flip flop 审中-公开
标题翻译：具有动态触发器信号电平位移的主锁存电路
公开(公告)号：US20060273838A1
公开(公告)日：2006-12-07
申请号：US10563040
申请日：2004-09-03
申请人： Jorg Berthold , Georg Jeorgakos , Stephan Henzler , Doris Schmitt-Landsiedel
发明人： Jorg Berthold , Georg Jeorgakos , Stephan Henzler , Doris Schmitt-Landsiedel
IPC分类号： H03H11/26
CPC分类号： H03K3/037 , H03K3/356121
摘要： A master latch circuit (10) with signal level displacement for a flip-flop (1) clocked by a clock pulse signal (Clk), wherein the master latch circuit (10) comprises a signal delay circuit (13) which delays and inverts the clock pulse signal (ClK) resulting in a specific time delay (AT), and a circuit node (14) which, in a charging phase wherein the clock pulse signal (Clk) is logically low, is charged to an operational voltage (VB) an which, in an evaluation phase when the clock pulse signal (Clk) and delayed, inverted clock pulse signal (Clk DELAY ) are logically high, is discharged according to a specific data signal (D), wherein the data signal controls only transistors of a single type (either only N-channel or only P-channel). The master latch circuit (10) has only one supply voltage.
摘要翻译：一种具有由时钟脉冲信号（Clk）时钟的触发器（1）的信号电平位移的主锁存电路（10），其中主锁存电路（10）包括信号延迟电路（13），其延迟和反相导致特定时间延迟（AT）的时钟脉冲信号（ClK）和在时钟脉冲信号（Clk）在逻辑上低的充电阶段被充电到工作电压（VB）的电路节点（14）当在时钟脉冲信号（Clk）和延迟的反相时钟脉冲信号（Clk DELAY ）在逻辑上为高时，在根据特定数据信号（D）放电的评估阶段中，数据信号仅控制单一类型的晶体管（仅N沟道或仅P通道）。主锁存电路（10）只有一个电源电压。

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