专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090167771A1 Methods and apparatuses for Configuring and operating graphics processing units 有权
标题翻译：用于配置和操作图形处理单元的方法和设备
公开(公告)号：US20090167771A1
公开(公告)日：2009-07-02
申请号：US12006015
申请日：2007-12-28
申请人： Itay Franko , Anshuman Thakur
发明人： Itay Franko , Anshuman Thakur
IPC分类号： G06F15/16
CPC分类号： G06T1/20
摘要： A graphics processing system with multiple graphics processing cores (GPC)s is disclosed. The apparatus can include a peripheral component interface express (PCIe) switch to interface the GPCs to a host processor. The apparatus can also include a transparent bus to connect the GPCs. The transparent bus can be implemented with two PCIe endpoints on each side of a nontransparent bridge where these three components provide a bus interconnect and a control line interconnect between the GPCs. Other embodiments are also disclosed.
摘要翻译：公开了具有多个图形处理核心（GPC）的图形处理系统。该装置可以包括用于将GPC与主机处理器连接的外围组件接口快速（PCIe）开关。该装置还可以包括用于连接GPC的透明总线。透明总线可以在非透明桥两侧的两个PCIe端点实现，这三个组件提供总线互连和GPC之间的控制线互连。还公开了其他实施例。

2. 发明授权

US08711153B2 Methods and apparatuses for configuring and operating graphics processing units 有权
标题翻译：用于配置和操作图形处理单元的方法和设备
公开(公告)号：US08711153B2
公开(公告)日：2014-04-29
申请号：US12006015
申请日：2007-12-28
申请人： Itay Franko , Anshuman Thakur
发明人： Itay Franko , Anshuman Thakur
IPC分类号： G06F15/16
CPC分类号： G06T1/20
摘要： A graphics processing system with multiple graphics processing cores (GPC)s is disclosed. The apparatus can include a peripheral component interface express (PCIe) switch to interface the GPCs to a host processor. The apparatus can also include a transparent bus to connect the GPCs. The transparent bus can be implemented with two PCIe endpoints on each side of a nontransparent bridge where these three components provide a bus interconnect and a control line interconnect between the GPCs. Other embodiments are also disclosed.
摘要翻译：公开了具有多个图形处理核心（GPC）的图形处理系统。该装置可以包括用于将GPC与主机处理器连接的外围组件接口快速（PCIe）开关。该装置还可以包括用于连接GPC的透明总线。透明总线可以在非透明桥两侧的两个PCIe端点实现，这三个组件提供总线互连和GPC之间的控制线互连。还公开了其他实施例。

3. 发明申请

US20140180457A1 ELECTRONIC DEVICE TO ALIGN AUDIO FLOW 审中-公开
标题翻译：电子设备对齐音频流
公开(公告)号：US20140180457A1
公开(公告)日：2014-06-26
申请号：US13727410
申请日：2012-12-26
申请人： Anshuman Thakur , Michael N. Derr , Hema Tahilramani , Andrzej Mialkowski
发明人： Anshuman Thakur , Michael N. Derr , Hema Tahilramani , Andrzej Mialkowski
IPC分类号： G06F17/00
CPC分类号： G06F1/3215 , G06F3/165
摘要： An electronic device is provided that includes an input device to provide first audio signals, an output device to receive second audio signals, and logic to receive the first audio signals and to provide an audio input flow. The logic to further receive an audio output flow and to provide the second audio signals to the output device based on the audio output flow. The audio device to further align the audio input flow relative to the audio output flow.
摘要翻译：提供一种电子设备，其包括用于提供第一音频信号的输入设备，用于接收第二音频信号的输出设备和用于接收第一音频信号的逻辑并提供音频输入流。进一步接收音频输出流并基于音频输出流向输出设备提供第二音频信号的逻辑。音频设备，用于进一步对准音频输入流相对于音频输出流。

4. 发明申请

US20140156896A1 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER IDENTIFIER (APIC ID) ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT 有权
标题翻译：高级可编程中断控制器标识符（APIC ID）多核处理单元的分配
公开(公告)号：US20140156896A1
公开(公告)日：2014-06-05
申请号：US13994104
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.
摘要翻译：在重新启动或重启包含多核处理器的系统之后，多核处理器可以为每个活动和合格的核心分配唯一的高级可编程中断控制器（APIC）标识符（ID）。初始化逻辑可以将多个处理核心中的每一个的状态检测为活动或不活动。初始化逻辑可以检测多个处理核心中的每个处理核心的属性符合分配APIC ID的资格，或者不符合APIC ID分配的资格。

5. 发明申请

US20220014202A1 Three-Dimensional Stacked Programmable Logic Fabric and Processor Design Architecture 有权
公开(公告)号：US20220014202A1
公开(公告)日：2022-01-13
申请号：US17485119
申请日：2021-09-24
申请人： Rahul Pal , Dheeraj Subbareddy , Mahesh Kumashikar , Dheemanth Nagaraj , Rajesh Vivekanandham , Anshuman Thakur , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
发明人： Rahul Pal , Dheeraj Subbareddy , Mahesh Kumashikar , Dheemanth Nagaraj , Rajesh Vivekanandham , Anshuman Thakur , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
IPC分类号： H03K19/17796 , G06F15/78 , G06F30/34 , H03K19/17758
摘要： The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.

6. 发明授权

US09367329B2 Initialization of multi-core processing system 有权
标题翻译：多核处理系统的初始化
公开(公告)号：US09367329B2
公开(公告)日：2016-06-14
申请号：US13993573
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas
IPC分类号： G06F9/24 , G06F15/177 , G06F9/44 , G06F1/24 , G06F11/07 , G06F13/14 , G06F15/80 , G06F12/08 , G06F13/00
CPC分类号： G06F9/4405 , G06F1/24 , G06F9/4403 , G06F11/0724 , G06F12/0813 , G06F13/00 , G06F13/14 , G06F15/177 , G06F15/80
摘要： This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type.
摘要翻译：本公开涉及使用共享的初始化和配置向量，其被传递到使用分组的多核处理器中的处理核心。初始化核心可以包括复位逻辑，其可以从集中存储位置读取初始化和配置向量，集中存储位置可以在包含处理核心（例如，熔丝等）的管芯上，例如在易失性存储器中，闪存等），或两者的组合。初始化内核然后可以生成分组以将初始化和配置向量传送到等待初始化（例如，重置之后）的处理核。在一些情况下，初始化和配置向量信息可以由相同类型的两个或多个核共享。

7. 发明申请

US20140006767A1 BOOT STRAP PROCESSOR ASSIGNMENT FOR A MULTI-CORE PROCESSING UNIT 有权
标题翻译：用于多核处理单元的引导带处理器分配
公开(公告)号：US20140006767A1
公开(公告)日：2014-01-02
申请号：US13993310
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Charan Sundararaman , Ramon Matas , Jay S. Lawlor , Robert F. Netting
IPC分类号： G06F9/44
CPC分类号： G06F9/4405 , G06F15/177
摘要： Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.
摘要翻译：在重新启动或重新启动包括多核处理器的系统之后，多核处理器可以将一个核心分配为引导带处理器（BSP）。初始化逻辑可以将多个处理核心中的每一个的状态检测为活动或不活动。初始化逻辑可以检测多个处理核心中的每一个的属性被认定为被分配为BSP，或者不符合被分配为BSP的资格。初始化逻辑可以至少部分地基于状态来检测作为活动处理核心的互连中的多个处理核心的最后处理核心，并且至少部分地基于该属性将其分配为BSP。在各种实施例中，初始化信息可以将最后的处理核分配为BSP。

8. 发明授权

US08335875B1 System and method for performing isochronous data buffering 失效
标题翻译：用于执行同步数据缓冲的系统和方法
公开(公告)号：US08335875B1
公开(公告)日：2012-12-18
申请号：US13168400
申请日：2011-06-24
申请人： Anshuman Thakur , Abdul R. Ismail
发明人： Anshuman Thakur , Abdul R. Ismail
IPC分类号： G06F3/00 , G06F5/00 , G06F15/16
CPC分类号： H04W52/0209 , Y02D70/142 , Y02D70/144 , Y02D70/23
摘要： A controller for a host system includes an interface and a buffer. The interface receives a plurality of data units isochronously received from a connected device, and the buffer stores the data units and then output a data block upon the occurrence of at least one condition. Each data unit stores data of a first size and the data block includes data of a second size greater than the first size. The connected device may be a Universal Serial Bus (USB) device or another type of device.
摘要翻译：用于主机系统的控制器包括接口和缓冲器。接口接收从连接的设备等时接收的多个数据单元，并且缓冲器存储数据单元，然后在发生至少一个条件时输出数据块。每个数据单元存储第一大小的数据，并且数据块包括大于第一大小的第二大小的数据。连接的设备可以是通用串行总线（USB）设备或其他类型的设备。

9. 发明授权

US09208124B2 Reset of processing core in multi-core processing system 有权
标题翻译：复核处理核心在多核处理系统中
公开(公告)号：US09208124B2
公开(公告)日：2015-12-08
申请号：US13993663
申请日：2011-12-29
申请人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas
发明人： Steven S. Chang , Anshuman Thakur , Ramacharan Sundararaman , Ramon Matas
IPC分类号： G06F11/00 , G06F15/80 , G06F13/14 , G06F1/24 , G06F11/07
CPC分类号： G06F15/80 , G06F1/24 , G06F11/0709 , G06F11/0724 , G06F11/0757 , G06F13/14
摘要： This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.
摘要翻译：本公开涉及在多核处理器中保持至少一个其他核的操作的同时执行一个或多个核的受控复位。初始化核心可以包括可以检测无响应的核心或核心的复位逻辑，或者否则其不能正常操作。初始化核心可以生成能够与有问题的核心进行通信的分组。初始化核心可以向有问题的核心发送重置分组，以指示有问题的核心执行复位。

10. 发明申请

US20150178291A1 WIRELESS DISPLAY WITH AUDIO SKIPPING 审中-公开
标题翻译：无线显示带音频跳线
公开(公告)号：US20150178291A1
公开(公告)日：2015-06-25
申请号：US14136696
申请日：2013-12-20
申请人： Inching Chen , Chinh T. Cao , Sherine Abdelhak , Anshuman Thakur
发明人： Inching Chen , Chinh T. Cao , Sherine Abdelhak , Anshuman Thakur
IPC分类号： G06F17/30
CPC分类号： H04N21/4122 , H04N21/4394 , H04N21/4396
摘要： This disclosure describes systems, methods, and computer-readable media related to wireless displays with audio skipping. In some embodiments, a plurality of audio packets may be captured. Each of the plurality of audio packets may be analyzed. Analyzing the packets may include determining whether an audio packet of the plurality of audio packets is silent. In response to determining the audio packet of the plurality of audio packets is not silent, an audio non-skip mode may be entered. In response to determining the audio packet of the plurality of audio packets is silent, a determination may be made as to whether an indicator has exceeded a threshold. The indicator may indicate a sequential number of silent audio packets. In response to the indicator indicating the indicator exceeds the threshold, an audio skip mode may be entered. In response to the indicator indicating the indicator has not exceeded the threshold, the audio non-skip mode may be entered.
摘要翻译：本公开描述了与具有跳过音频的无线显示器相关的系统，方法和计算机可读介质。在一些实施例中，可以捕获多个音频分组。可以分析多个音频分组中的每一个。分析分组可以包括确定多个音频分组的音频分组是否是静音的。响应于确定多个音频分组的音频分组不是静音，可以输入音频非跳过模式。响应于确定多个音频分组的音频分组是静音，可以确定指示符是否已经超过阈值。指示符可以指示静音音频分组的顺序数量。响应于指示指示符超过阈值的指示符，可以输入音频跳过模式。响应于指示符指示符未超过阈值的指示符，可以输入音频非跳过模式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式