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1. 发明授权

US4525776A Arithmetic logic unit arranged for manipulating bits 失效
标题翻译：布置用于操纵位的算术逻辑单元
公开(公告)号：US4525776A
公开(公告)日：1985-06-25
申请号：US155317
申请日：1980-06-02
申请人： Ismail I. Eldumiati , Michael K. Maul
发明人： Ismail I. Eldumiati , Michael K. Maul
IPC分类号： G06F7/00 , G06F7/76 , G06F9/308 , G06F15/20
CPC分类号： G06F7/762 , G06F9/30018
摘要： A digital computer is arranged to process data through an arithmetic logic unit in response to instructions residing sequentially in an instruction register, each instruction requiring a single instruction interval for fetching data from a selected source in a store, processing the data in the arithmetic logic unit, and storing the result of processing the data into a selected destination in the store. Means are provided for moving a single bit from any selected one of a plurality of bit positions in the selected source to any selected bit position of a plurality of bit positions in the selected destination during a single instruction interval without affecting the state of any other bit of the selected destination.
摘要翻译：数字计算机被设置为响应于顺序地驻留在指令寄存器中的指令来处理数据，每个指令需要单个指令间隔，用于从存储器中的所选源提取数据，处理算术逻辑单元中的数据并将数据处理的结果存储在存储器中的所选择的目的地中。提供了用于在单个指令间隔期间将单个位从所选择的源中的多个比特位置中的任何一个位置移动到所选择的目的地中的多个比特位置的任何选定比特位置的装置，而不影响任何其他比特的状态的所选目的地。

2. 发明授权

US4230958A Loss of clock detector circuit 失效
标题翻译：时钟检测电路丢失
公开(公告)号：US4230958A
公开(公告)日：1980-10-28
申请号：US932266
申请日：1978-08-09
申请人： Harry J. Boll , Michael K. Maul
发明人： Harry J. Boll , Michael K. Maul
IPC分类号： H03K5/19
CPC分类号： H03K5/19
摘要： This invention involves a detector circuit in MOS technology for sensing "loss of clock"; that is, whenever a clock input voltage pulse source is interrupted or stops (becomes "stuck") at any level, the output voltage of the detector circuit is at a high level, but is at a low level when the clock is working properly. Such a circuit is achieved by means of a first MOS electrical inverter (I.sub.1), connected for feeding its output to an MOS electrical differentiator (.DELTA.), connector for feeding its output to a thresholding MOS amplifier (A), connected for feeding its output to a unidirectional MOS current inhibitor (D), connected for feeding its output to a second MOS electrical inverter (I.sub.2), connected in parallel with a storage capacitor (C) in parallel with a leakage current source (J.sub.L), whereby the output of the second inverter is a binary indication of the presence vs. absence of clock pulse input to the first inverter.
摘要翻译：本发明涉及用于感测“时钟损失”的MOS技术中的检测器电路; 也就是说，每当时钟输入电压脉冲源中断或停止（变为“卡住”）任何电平时，检测器电路的输出电压处于高电平，但是当时钟正常工作时处于低电平。这样的电路通过连接用于将其输出馈送到MOS电差分器（DELTA）的第一MOS电逆变器（I1）来实现，连接器用于将其输出馈送到阈值MOS放大器（A），连接用于馈送其输出连接到用于将其输出馈送到与漏电流源（JL）并联的与存储电容器（C）并联连接的第二MOS电逆变器（I2）的单向MOS电流抑制器（D），由此，第二反相器是输入到第一反相器的时钟脉冲的存在与否的二进制指示。

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