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    • 5. 发明授权
    • Arithmetic logic unit arranged for manipulating bits
    • 布置用于操纵位的算术逻辑单元
    • US4525776A
    • 1985-06-25
    • US155317
    • 1980-06-02
    • Ismail I. EldumiatiMichael K. Maul
    • Ismail I. EldumiatiMichael K. Maul
    • G06F7/00G06F7/76G06F9/308G06F15/20
    • G06F7/762G06F9/30018
    • A digital computer is arranged to process data through an arithmetic logic unit in response to instructions residing sequentially in an instruction register, each instruction requiring a single instruction interval for fetching data from a selected source in a store, processing the data in the arithmetic logic unit, and storing the result of processing the data into a selected destination in the store. Means are provided for moving a single bit from any selected one of a plurality of bit positions in the selected source to any selected bit position of a plurality of bit positions in the selected destination during a single instruction interval without affecting the state of any other bit of the selected destination.
    • 数字计算机被设置为响应于顺序地驻留在指令寄存器中的指令来处理数据,每个指令需要单个指令间隔,用于从存储器中的所选源提取数据,处理算术逻辑单元中的数据 并将数据处理的结果存储在存储器中的所选择的目的地中。 提供了用于在单个指令间隔期间将单个位从所选择的源中的多个比特位置中的任何一个位置移动到所选择的目的地中的多个比特位置的任何选定比特位置的装置,而不影响任何其他比特的状态 的所选目的地。
    • 7. 发明授权
    • Interrupt controller arrangement for mutually exclusive interrupt
signals in data processing systems
    • 用于数据处理系统中互斥中断信号的中断控制器布置
    • US4761732A
    • 1988-08-02
    • US802988
    • 1985-11-29
    • Ismail I. EldumiatiDavid T. MelnikRobert P. Wiederhold
    • Ismail I. EldumiatiDavid T. MelnikRobert P. Wiederhold
    • G06F13/24
    • G06F13/24
    • An interrupt controller circuit arrangement is used for encoding and storing "interrupt" signals indicating random (asynchronous) occurrence of corresponding events and for delivering corresponding "interrupt" (alarm command) signals to a (synchronous) microprocessor corresponding to the events as they occur. The events are divided into two (or more) sets in order to reduce the required number of latches and to increase the speed of operation. One (or more) of these sets consists of events which never can occur "simultaneously" (i.e., which are mutually exclusive in the sense that (within each of such sets) not more than a single one of the events can occur--and can occur only once--within a prescribed amount of time); the remaining set consists of the remaining events--i.e., those which can occur "simultaneously" or can occur simultaneously with one or more of those in the other set(s). In this way only the interrupt signals indicating the occurrence of events in the remaining set need be individually latched in separate latches each of which is devoted to a separate one of the events in that set.
    • 中断控制器电路装置用于编码和存储指示对应事件的随机(异步)发生的“中断”信号,并用于将相应的“中断”(报警命令)信号传送到对应于事件发生的(同步)微处理器。 事件被分为两个(或多个)集合,以便减少所需的锁存数量并提高操作速度。 这些集合中的一个(或多个)由不能“同时”发生的事件组成(即,在这些集合中的每个集合内,不超过一个事件可以发生的意义上,这些事件是相互排斥的,并且可以 仅在一定时间内发生一次); 剩余的组由剩余事件组成,即可同时发生的事件,或者可以与另一组中的一个或多个同时发生。 以这种方式,只有指示剩余集中的事件发生的中断信号需要单独锁存在单独的锁存器中,每个锁存器专用于该集合中的事件的单独一个。
    • 8. 发明授权
    • Conditional transfer control circuit
    • 条件转移控制电路
    • US4310881A
    • 1982-01-12
    • US77613
    • 1979-09-21
    • Ismail I. Eldumiati
    • Ismail I. Eldumiati
    • G06F9/32G06F13/00
    • G06F9/30058
    • In a conditional transfer control circuit (10) for a controller (11) arranged for fetching instructions from a sequence of addresses wherein a list of instructions is stored, there is a circuit (25) for producing a first signal (C) representing a true or false condition resulting from executing an instruction in the list of instructions and a circuit (IRO) for producing applying a second signal (on lead 32 or 72) indicating whether control is determined by the first signal being true or by the first signal being false. An EXCLUSIVE NOR (or EXCLUSIVE OR) gate (30 or 70), responsive to the first and second signals, produces a condition transfer signal (on lead 18) that causes the controller to fetch a next subsequent instruction from an address other than the next subsequent address in the sequence of addresses wherein the list of instructions is stored.
    • 在用于从存储指令列表的地址序列中取出指令的用于控制器(11)的条件转移控制电路(10)中,存在用于产生表示真实的第一信号(C)的电路(25) 或执行指令列表中的指令产生的假条件和用于产生指示是否由第一信号确定控制或由第一信号为假的第二信号(在引线32或72上)产生的电路(IRO) 。 响应于第一和第二信号的EXCLUSIVE NOR(或EXCLUSIVE OR)门(30或70)产生条件转移信号(在引线18上),使得控制器从除下一个地址以外的地址获取下一个后续指令 其中存储指令列表的地址序列中的后续地址。