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1. 发明授权

US4434491A Semiconductor laser 失效
标题翻译：半导体激光器
公开(公告)号：US4434491A
公开(公告)日：1984-02-28
申请号：US248157
申请日：1981-03-30
申请人： Isamu Sakuma , Katsuhiko Nishida , Hideo Kawano , Masayasu Ueno , Yoshishige Matsumoto , Shohei Matsumoto , Takao Furuse
发明人： Isamu Sakuma , Katsuhiko Nishida , Hideo Kawano , Masayasu Ueno , Yoshishige Matsumoto , Shohei Matsumoto , Takao Furuse
IPC分类号： H01S5/223 , H01S3/19
CPC分类号： H01S5/2232 , H01S5/2234
摘要： A semiconductor laser of the rib guide type having the thickness of an active layer within a stripe-shaped region thicker than that of the outside, and thus the stripe-shaped region is made to have a waveguide action and, thereby, fundamental mode laser may be achieved.
摘要翻译：肋引导型的半导体激光器具有比外部厚的条形区域内的有源层的厚度，并且因此使条形区域具有波导作用，因此基模激光器实现。

2. 发明授权

US08054436B2 Substrate for display device and display device 有权
标题翻译：基板用于显示设备和显示设备
公开(公告)号：US08054436B2
公开(公告)日：2011-11-08
申请号：US11904232
申请日：2007-09-26
申请人： Hideo Kawano , Hideki Sunayama
发明人： Hideo Kawano , Hideki Sunayama
IPC分类号： G02F1/1345
CPC分类号： G02F1/136204 , Y10T29/49002
摘要： A substrate for display device is provided. As a wiring structure of the substrate, the scan line layer and the signal line layer are not connected directly by arranging through-holes between the scan line layer and the signal line layer, but are connected through an ITO layer by arranging through-holes between the scan line layer and the ITO layer and arranging through-holes between the signal line layer and the ITO layer, with an object to reduce the value of the connection resistance between the scan line layer and the signal line layer. Through-holes connecting the scan line layer and the ITO layer and through-holes connecting the signal line layer and the ITO layer are configured in a comb shape respectively and engaged with each other. Thus the length of the ITO connecting the scan line layer and the signal line layer becomes shorter and the value of the connection resistance is reduced.
摘要翻译：提供了一种显示装置用基板。作为基板的布线结构，通过在扫描线层和信号线层之间设置通孔而不直接连接扫描线层和信号线层，而是通过在ITO层之间布置通孔而连接扫描线层和ITO层，并且在信号线层和ITO层之间布置通孔，目的是减少扫描线层和信号线层之间的连接电阻的值。连接扫描线层和ITO层的通孔和连接信号线层和ITO层的通孔分别配置为梳形并彼此接合。因此，连接扫描线层和信号线层的ITO的长度变短，连接电阻值降低。

3. 发明授权

US4148971A Flame spraying materials and process for producing the same 失效
标题翻译：火焰喷涂材料及其制造方法
公开(公告)号：US4148971A
公开(公告)日：1979-04-10
申请号：US830498
申请日：1977-09-06
申请人： Hideo Kawano , Oelschlagel Dietrich , Katumi Nakata , Kenkichi Yamaji
发明人： Hideo Kawano , Oelschlagel Dietrich , Katumi Nakata , Kenkichi Yamaji
IPC分类号： C23C4/08 , B05D1/08 , B22F7/08 , B32B15/02
CPC分类号： C23C4/08 , Y10T428/12097 , Y10T428/12222 , Y10T428/12403
摘要： A flame spraying material consisting of a wire obtained by compacting zinc powder, zinc-aluminum alloy powder or admixed powders of zinc and aluminum or consisting of a composite wire obtained by enclosing said compacted powders in an aluminum covering.
摘要翻译：一种火焰喷涂材料，其由通过压实锌粉，锌铝合金粉末或锌和铝的混合粉末或由通过将所述压实粉末包封在铝覆盖物中而获得的复合线材而获得的线材组成。

4. 发明授权

US09244315B2 Active matrix display device 有权
标题翻译：主动矩阵显示装置
公开(公告)号：US09244315B2
公开(公告)日：2016-01-26
申请号：US14343419
申请日：2012-05-30
申请人： Hideo Kawano
发明人： Hideo Kawano
IPC分类号： G02F1/1343 , G09G3/36 , H01L27/32 , H01L27/12 , G02F1/1362 , H01L29/417
CPC分类号： G02F1/134336 , G02F1/13439 , G02F1/1362 , G09G3/3648 , G09G2300/0417 , G09G2300/0819 , G09G2300/0852 , G09G2320/0247 , H01L27/1225 , H01L27/1255 , H01L27/3276 , H01L29/41733
摘要： To restrain decrease of display quality because of increases in flicker level and decrease of uniformity in screen luminance caused by increases in the overcharging effect when an amorphous metal oxide semiconductor or an organic semiconductor that has an field-effect mobility greater than amorphous silicon is used for pixel TFTs in a liquid crystal display device or organic EL display device. A new relational formula is derived for punch-through voltage in gray scale display, where the visibility of flicker, screen burn-in, and the like is high, and in-plane differential in counter electrode potential, which are an index of the overcharging effect. A design is made so as to satisfy conditions for decreasing the in-plane differential in counter electrode potential that have been newly derived on the basis of this formula to an allowable limit value or less.
摘要翻译：为了抑制由于使用非晶态金属氧化物半导体或具有大于非晶硅的场效应迁移率的有机半导体而使过度充电效果增加而引起的闪烁水平增加和屏幕亮度均匀性降低的显示质量降低液晶显示装置或有机EL显示装置中的像素TFT。导出了灰度显示中的穿透电压的新关系公式，其中闪烁，屏幕老化等的可视性高，并且对电极电位的面内差异是过度充电的指标影响。进行设计以满足将根据该公式新近导出的对置电极的面内差异减小到允许极限值以下的条件。

5. 发明授权

US08633038B2 Manufacturing method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US08633038B2
公开(公告)日：2014-01-21
申请号：US13552068
申请日：2012-07-18
申请人： Hideo Kawano , Haruko Tamegai , Tooru Yashima
发明人： Hideo Kawano , Haruko Tamegai , Tooru Yashima
IPC分类号： H01L21/66
CPC分类号： H01L24/05 , G01R1/06755 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0401 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13076 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2224/11 , H01L2924/00 , H01L2924/01047 , H01L2924/00012 , H01L2924/01083 , H01L2924/01029 , H01L2924/01051 , H01L2924/01074 , H01L2224/05552
摘要： In wafer probe inspection for a flip-chip semiconductor device having a solder bump, electric test may be performed at a high temperature by causing a probe needle to directly contact a solder bump over a wafer. The inventors have examined such high temperature probe tests in various ways and revealed the following problems. When a high temperature probe test is performed at 90° C. or higher using a palladium alloy probe needle, tin diffusion due to a solder bump occurs at the needle point to raise resistance, resulting in causing open failure. According to the invention of the present application, at least the tip of a palladium-based probe needle has mainly a granular grain structure in a high temperature probe test performed with the palladium-based probe needle contacting a solder bump electrode over a semiconductor wafer.
摘要翻译：在具有焊料凸块的倒装芯片半导体器件的晶片探针检查中，可以通过使探针直接接触晶片上的焊料凸块，在高温下进行电测试。本发明人以各种方式检查了这种高温探针测试，并显示出以下问题。当使用钯合金探针在90℃以上进行高温探针试验时，由于焊点发生锡扩散，从而引起电阻升高，导致开路故障。根据本申请的发明，在钯类探针与半导体晶片上的焊料凸块电极接触的高温探针试验中，钯系探针的至少顶端主要具有粒状结构。

6. 发明授权

US06250536B1 Method for manufacturing electrode wire for electrical discharge machining apparatus 有权
标题翻译：放电加工用电极线的制造方法
公开(公告)号：US06250536B1
公开(公告)日：2001-06-26
申请号：US09311531
申请日：1999-05-13
申请人： Kiyoshi Shimojima , Seigi Aoyama , Hideo Kawano , Koichi Tamura , Takahiro Sato , Takamitsu Kimura , Masato Watabe
发明人： Kiyoshi Shimojima , Seigi Aoyama , Hideo Kawano , Koichi Tamura , Takahiro Sato , Takamitsu Kimura , Masato Watabe
IPC分类号： B21D2100
CPC分类号： B23H7/08
摘要： The invention relates to a method for manufacturing an electrode wire for an electrical discharge machining apparatus, which is composed of a core wire formed of Cu or Cu-alloy and a covering layer formed of brass. A brass tape is longitudinally applied around a core wire to provide a pipe, a seam formed by butting longitudinal edges of the brass tape is continuously welded to provide a composite wire, area-reduction process of reduction rate less than 65% is applied to the brass pipe by means of a squeezing die, a heat treatment at a temperature higher a recrystallization one of brass is applied to the composite pipe, and thereafter the composite wire is processed to be reduced in area through plural reducing dies step by step.
摘要翻译：本发明涉及一种用于制造放电加工装置的电极线的方法，该方法由由Cu或Cu合金形成的芯线和由黄铜形成的覆盖层组成。黄铜带纵向施加在芯线周围以提供管道，通过对接黄铜带的纵向边缘而形成的接缝被连续地焊接以提供复合线，减少率小于65％的面积减小过程被应用于黄铜管通过挤压模具进行热处理，在复合管上施加黄铜重结晶的温度较高的热处理，然后通过多个还原模具逐步加工复合线的面积。

7. 发明授权

US5835177A Array substrate with bus lines takeout/terminal sections having multiple conductive layers 失效
标题翻译：具有总线线路的阵列基板取出/端子部分具有多个导电层
公开(公告)号：US5835177A
公开(公告)日：1998-11-10
申请号：US726472
申请日：1996-10-04
申请人： Masayuki Dohjo , Hideo Kawano , Akira Kubo , Makoto Shibusawa , Tetsuya Iizuka , Tamio Nakai , Kazushige Mori
发明人： Masayuki Dohjo , Hideo Kawano , Akira Kubo , Makoto Shibusawa , Tetsuya Iizuka , Tamio Nakai , Kazushige Mori
IPC分类号： G02F1/13 , G02F1/1345 , G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , G02F1/1343 , H01L29/04
CPC分类号： G02F1/13458 , G02F1/1345 , G02F1/13452 , G02F1/136213 , G02F1/136227 , H01L27/1214 , G02F2001/13629
摘要： An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127). With such an arrangement, an appropriate storage capacitor can be formed by causing the scanning lines and pixel electrode to overlap each other without having to decrease the manufacturing yield while enabling achievement of high aperture ratio.
摘要翻译：阵列基板包括多个扫描线（111）; 具有第一介电膜（115），（117），其上的半导体膜（120）和与半导体膜（120）电耦合的源电极（126b）和漏电极（126a）的薄膜晶体管（112））; 从所述漏电极（126a）取出以与所述扫描线（111）大致直角延伸的信号线（110）。以及与源电极（126b）电连接的像素电极（131），其中像素电极（131）通过设置在至少信号线上的第二电介质膜（127）与源电极（126b）电连接（110），而像素电极（131）通过第一和第二介电膜（115），（117），（127）与其相邻扫描线（111）的细长区域（113）重叠。通过这样的布置，可以通过使扫描线和像素电极彼此重叠而不必降低制造成品率而能够实现高开口率而形成适当的存储电容器。

8. 发明申请

US20080074571A1 Display device and manufacturing method thereof 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20080074571A1
公开(公告)日：2008-03-27
申请号：US11900246
申请日：2007-09-11
申请人： Hideo Kawano , Hideki Sunayama
发明人： Hideo Kawano , Hideki Sunayama
IPC分类号： G02F1/1343
CPC分类号： G02F1/136286 , G02F1/136204 , G02F1/136213
摘要： The object of the present invention is to provide a liquid crystal display device, which can be used in the active matrix type liquid crystal display device and has a wiring structure of superfine wiring, and a method for manufacturing the liquid crystal display device, wherein it can reduce the occurrence rate of the failures caused by the static electricity which damages the insulating layer of the electrodes or between the electrodes in the manufacturing process, and the time constant of the scan line can be improved simultaneously. In the manufacturing process for the array substrate, the wiring width in the portions of the scan line where the scan lines intersect the auxiliary capacitance bunching lines is narrowed, meanwhile, the area of the portions where the scan lines intersect the auxiliary capacitance bunching lines is reduced, and the wiring capacitance is reduced, the time constant of the scan line is decreased, meanwhile, the wiring width in portions of the auxiliary capacitance lines where they intersect the auxiliary capacitance bunching line is enlarged, the distance between the adjacent scan line and the nearest portion of the auxiliary capacitance line is shortened, and the static charges brought by the manufacturing process, and the like, discharge at the nearest portion, and the failure products caused by the static damage during the manufacturing process can be prevented from occurring.
摘要翻译：本发明的目的是提供一种可用于有源矩阵型液晶显示装置并具有超细布线的布线结构的液晶显示装置和液晶显示装置的制造方法，其中可以降低在制造过程中由于电极绝缘层或电极之间的静电引起的故障的发生率，并且可以同时提高扫描线的时间常数。在阵列基板的制造工序中，扫描线与辅助电容聚束线相交的扫描线的部分的布线宽度变窄，同时扫描线与辅助电容聚束线相交的部分的面积为并且布线电容减小，扫描线的时间常数减小，同时辅助电容线的与辅助电容聚束线相交的部分的布线宽度增大，相邻的扫描线与辅助电容线的最近部分被缩短，并且由制造过程引起的静电等等在最近部分放电，并且可以防止在制造过程中由静电损伤引起的故障产物。

9. 发明授权

US06380591B1 Electrode wiring board subjected to counter measure against static electricity and display device using the same 有权
标题翻译：对静电进行对抗的电极接线板及使用其的显示装置
公开(公告)号：US06380591B1
公开(公告)日：2002-04-30
申请号：US09198530
申请日：1998-11-24
申请人： Hideo Kawano
发明人： Hideo Kawano
IPC分类号： H01L2940
CPC分类号： G02F1/136204
摘要： A step portion is formed in an insulating layer provided between two opposing electrode layers outside a pixel electrode formation region, so that a projection portions are formed on the two electrode layers, wherein the shape of the projection portions of the electrode layers is of an electric-field concentration type to induce discharging between the opposing portions of the layers via the insulating layer.
摘要翻译：在设置在像素电极形成区域外部的两个相对电极层之间的绝缘层中形成台阶部分，使得在两个电极层上形成突起部分，其中电极层的突出部分的形状为电场浓度型，以经由绝缘层诱导层的相对部分之间的放电。

10. 发明授权

US6078366A Array substrate comprising semiconductor contact layers having same outline as signal lines 有权
标题翻译：阵列基板包括具有与信号线相同轮廓的半导体接触层
公开(公告)号：US6078366A
公开(公告)日：2000-06-20
申请号：US187422
申请日：1998-11-06
申请人： Masayuki Dohjo , Hideo Kawano , Akira Kubo , Makoto Shibusawa , Tetsuya Iizuka , Tamio Nakai , Kazushige Mori
发明人： Masayuki Dohjo , Hideo Kawano , Akira Kubo , Makoto Shibusawa , Tetsuya Iizuka , Tamio Nakai , Kazushige Mori
IPC分类号： G02F1/13 , G02F1/1345 , G02F1/1362 , H01L21/77 , H01L21/84 , H01L27/12 , G02F1/136 , G02F1/1343 , H01L29/04
CPC分类号： G02F1/13458 , G02F1/1345 , G02F1/13452 , G02F1/136213 , G02F1/136227 , H01L27/1214 , G02F2001/13629
摘要： An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127). With such an arrangement, an appropriate storage capacitor can be formed by causing the scanning lines and pixel electrode to overlap each other without having to decrease the manufacturing yield while enabling achievement of high aperture ratio.
摘要翻译：阵列基板包括多个扫描线（111）; 具有第一电介质膜（115），（117），其上的半导体膜（120）和与半导体膜（120）电耦合的源电极（126b）和漏电极（126a）的薄膜晶体管（112））; 从所述漏电极（126a）取出以与所述扫描线（111）大致直角延伸的信号线（110）。以及与源电极（126b）电连接的像素电极（131），其中像素电极（131）通过设置在至少信号线上的第二电介质膜（127）与源电极（126b）电连接（110），而像素电极（131）通过第一和第二介电膜（115），（117），（127）与其相邻扫描线（111）的细长区域（113）重叠。通过这样的布置，可以通过使扫描线和像素电极彼此重叠而不必降低制造成品率而能够实现高开口率而形成适当的存储电容器。

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