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1. 发明授权

US07842976B2 Semiconductor device having MOS transistors which are serially connected via contacts and conduction layer 有权
标题翻译：具有通过触点和导电层串联连接的MOS晶体管的半导体器件
公开(公告)号：US07842976B2
公开(公告)日：2010-11-30
申请号：US12259527
申请日：2008-10-28
申请人： Isamu Fujii , Shinichi Miyatake , Yuko Watanabe , Homare Sato
发明人： Isamu Fujii , Shinichi Miyatake , Yuko Watanabe , Homare Sato
IPC分类号： H01L27/10 , H01L29/73 , H01L29/74
CPC分类号： H01L27/0207 , H01L27/10885
摘要： A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes.
摘要翻译：半导体器件包括以预定间距排列的多条信号线; 连接到信号线的第一和第二MOS晶体管，并且彼此串联连接; 以及连接装置，其作为串联连接的第一和第二MOS晶体管之间的连接节点，并且将第一和第二MOS晶体管之一的源极区域连接到第一和第二MOS晶体管的另一个的漏极区域，经由通过绝缘层形成的接触孔和连接到接触孔的导电层。

2. 发明授权

US08331122B2 Semiconductor device and information processing system including the same 有权
标题翻译：半导体装置和信息处理系统也包括在内
公开(公告)号：US08331122B2
公开(公告)日：2012-12-11
申请号：US12923749
申请日：2010-10-06
申请人： Homare Sato , Junichi Hayashi
发明人： Homare Sato , Junichi Hayashi
IPC分类号： G11C5/02 , H01L23/12
CPC分类号： G11C11/408 , G11C7/1066 , H01L2224/13 , H01L2224/16145 , H01L2224/16225
摘要： A semiconductor device includes plural core chips and an interface chip that controls the plural core chips. Each of the plural core chips includes a layer address generating circuit that generates a second chip address by incrementing a value of a first chip address and a layer address comparing circuit that compares a third chip address supplied from the interface chip and the second chip address, and activates a chip selection signal when the third chip address and the second chip address are matched with each other. When a non-used chip signal is in an inactivated state, the layer address generating circuit supplies the second chip address to another core chip, and when the non-used chip signal is in an activated state, the layer address generating circuit supplies the first chip address to another core chip without a change.
摘要翻译：半导体器件包括多个核心芯片和控制多个芯片的接口芯片。多个核心芯片中的每一个包括通过增加第一芯片地址的值产生第二芯片地址的层地址产生电路和比较从接口芯片提供的第三芯片地址和第二芯片地址的层地址比较电路，并且当第三芯片地址和第二芯片地址彼此匹配时激活芯片选择信号。当未使用的芯片信号处于非激活状态时，层地址产生电路将第二芯片地址提供给另一核心芯片，并且当未使用的芯片信号处于激活状态时，层地址产生电路提供第一芯片芯片地址到另一个核心芯片没有变化。

3. 发明授权

US09378775B2 Semiconductor device including plural chips stacked to each other 有权
标题翻译：包括彼此堆叠的多个芯片的半导体装置
公开(公告)号：US09378775B2
公开(公告)日：2016-06-28
申请号：US13358448
申请日：2012-01-25
申请人： Junichi Hayashi , Homare Sato
发明人： Junichi Hayashi , Homare Sato
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C5/06 , G11C5/02
CPC分类号： G11C5/063 , G11C5/02
摘要： Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to the first chip. The second output circuit supplies the first command signal to the second chip. The third output circuit supplies a second command signal to the first and second chips.
摘要翻译：公开了这样的装置，其包括彼此堆叠的第一和第二芯片，以及控制堆叠在第一和第二芯片上的第一和第二芯片的第三芯片，并且包括第一，第二和第三输出电路。第一输出电路向第一芯片提供第一命令信号。第二输出电路将第一命令信号提供给第二芯片。第三输出电路向第一和第二芯片提供第二命令信号。

4. 发明申请

US20140153352A1 SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER 有权
标题翻译：半导体器件，其中包括堆叠在一起的其他一些
公开(公告)号：US20140153352A1
公开(公告)日：2014-06-05
申请号：US14175839
申请日：2014-02-07
申请人： Homare Sato
发明人： Homare Sato
IPC分类号： G11C11/4063
CPC分类号： G11C11/408 , G06F12/0207 , G06F12/0223 , G06F12/08 , G11C5/02 , G11C5/04 , G11C8/12 , G11C11/4063 , H01L23/481 , H01L25/18 , H01L2224/16145
摘要： A method for accessing a plurality of DRAM devices each having a plurality of banks, includes determining an operating mode for the plurality of DRAM devices, providing a chip selection address and a bank address with an active command to activate a first bank in a first one of the plurality of DRAM devices and, while the first bank in the first one of the plurality of DRAM devices is activated, one or more first banks in remaining DRAM devices of the plurality of DRAM devices are: not activated if the operating mode is determined to be a logical rank address mode, and possibly activated if the operating mode is determined to be a physical rank address mode, and subsequently providing at least a bank address with a column command to access the first bank in the first one of the plurality of DRAM devices.
摘要翻译：一种用于访问多个具有多个存储体的DRAM装置的方法，包括确定多个DRAM装置的操作模式，提供具有活动命令的芯片选择地址和存储体地址以激活第一组中的第一存储体并且当所述多个DRAM器件中的第一个DRAM器件中的第一存储体被激活时，所述多个DRAM器件的剩余DRAM器件中的一个或多个第一存储体是：如果所述操作模式被确定则不被激活作为逻辑秩地址模式，并且如果确定操作模式被确定为物理等级地址模式，则可能被激活，并且随后至少提供具有列命令的存储体地址以访问多个 DRAM设备。

5. 发明申请

US20110087835A1 Semiconductor memory device and data processing system 有权
标题翻译：半导体存储器件和数据处理系统
公开(公告)号：US20110087835A1
公开(公告)日：2011-04-14
申请号：US12923790
申请日：2010-10-07
申请人： Homare Sato , Junichi Hayashi
发明人： Homare Sato , Junichi Hayashi
IPC分类号： G06F12/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/4072 , G11C11/4076 , G11C16/20 , G11C2211/4061
摘要： To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation.
摘要翻译：包括预先给出彼此不同的芯片信息片段的多个核心芯片。第一刷新命令被分成具有彼此不同定时的多个第二刷新命令，并且对于其中第二刷新命令的计数值和芯片信息的至少一部分匹配的核心芯片执行刷新操作彼此。利用这种配置，即使当第二刷新命令被共同地提供给多个核心芯片时，也可以移动每个核心芯片中的刷新操作的定时。因此，可以减少刷新时的峰值电流。

6. 发明申请

US20070246440A1 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070246440A1
公开(公告)日：2007-10-25
申请号：US11785535
申请日：2007-04-18
申请人： Homare Sato
发明人： Homare Sato
IPC分类号： C23F1/00 , C03C25/68
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/122 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A semiconductor memory device is provided in which a phase-change layer can be formed stably and electric current required to cause the phase change of the phase-change layer can be reduced. An edge portion of the phase-change layer is formed above a lower electrode. The edge portion is formed to assume a tapered shape in cross section such that the thickness of the phase-change layer varies above the contact area between the lower electrode and the phase-change layer. The tapered portion is filled with an oxide film. According to this configuration, the region in which the phase-change occurs can be restricted, and hence the phase-change layer can be heated efficiently, resulting in reduction of electric current required for heating.
摘要翻译：提供一种半导体存储器件，其中可以稳定地形成相变层，并且可以减少引起相变层的相变所需的电流。相变层的边缘部分形成在下部电极的上方。边缘部形成为截面为锥形，使得相变层的厚度在下电极和相变层之间的接触面积之上变化。锥形部分填充有氧化膜。根据该结构，可以限制发生相变的区域，因此可以有效地加热相变层，导致加热所需的电流的降低。

7. 发明申请

US20070120128A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070120128A1
公开(公告)日：2007-05-31
申请号：US11602947
申请日：2006-11-22
申请人： Homare Sato , Kiyoshi Nakai
发明人： Homare Sato , Kiyoshi Nakai
IPC分类号： H01L27/108 , H01L29/00 , H01L31/036 , H01L31/112
CPC分类号： G11C13/003 , G11C11/5678 , G11C13/0004 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A semiconductor memory device includes a plurality of active regions, and a gate electrode in a fish bone shape arranged on each active region. In each active region, a plurality of source regions and a plurality of drain regions are arranged in a matrix manner. The source regions are commonly connected to a source line, and the drain regions are each connected to a lower electrode of a different memory element. According to the present invention, it is possible to assign three cell transistors connected in parallel to one memory element, so that an effective gate width is further increased.
摘要翻译：半导体存储器件包括多个有源区，以及布置在每个有源区上的鱼骨形状的栅电极。在每个有源区域中，以矩阵方式布置多个源极区域和多个漏极区域。源极区域通常连接到源极线，并且漏极区域各自连接到不同存储元件的下部电极。根据本发明，可以分配与一个存储元件并联的三个单元晶体管，从而进一步增加有效栅极宽度。

8. 发明授权

US08797822B2 Semiconductor device including plural chips stacked to each other 有权
标题翻译：包括彼此堆叠的多个芯片的半导体装置
公开(公告)号：US08797822B2
公开(公告)日：2014-08-05
申请号：US14175839
申请日：2014-02-07
申请人： Homare Sato
发明人： Homare Sato
IPC分类号： G11C8/00 , G06F12/02 , G06F12/08 , G11C8/12 , G11C5/02 , G11C5/04
CPC分类号： G11C11/408 , G06F12/0207 , G06F12/0223 , G06F12/08 , G11C5/02 , G11C5/04 , G11C8/12 , G11C11/4063 , H01L23/481 , H01L25/18 , H01L2224/16145
摘要： A method for accessing a plurality of DRAM devices each having a plurality of banks, includes determining an operating mode for the plurality of DRAM devices, providing a chip selection address and a bank address with an active command to activate a first bank in a first one of the plurality of DRAM devices and, while the first bank in the first one of the plurality of DRAM devices is activated, one or more first banks in remaining DRAM devices of the plurality of DRAM devices are: not activated if the operating mode is determined to be a logical rank address mode, and possibly activated if the operating mode is determined to be a physical rank address mode, and subsequently providing at least a bank address with a column command to access the first bank in the first one of the plurality of DRAM devices.
摘要翻译：一种用于访问多个具有多个存储体的DRAM装置的方法，包括确定多个DRAM装置的操作模式，提供具有活动命令的芯片选择地址和存储体地址以激活第一组中的第一存储体并且当所述多个DRAM器件中的第一个DRAM器件中的第一存储体被激活时，所述多个DRAM器件的剩余DRAM器件中的一个或多个第一存储体是：如果所述操作模式被确定则不被激活作为逻辑秩地址模式，并且如果确定操作模式被确定为物理等级地址模式，则可能被激活，并且随后至少提供具有列命令的存储体地址以访问多个 DRAM设备。

9. 发明授权

US08681525B2 Semiconductor device including plural chips stacked to each other 有权
标题翻译：包括彼此堆叠的多个芯片的半导体装置
公开(公告)号：US08681525B2
公开(公告)日：2014-03-25
申请号：US13347521
申请日：2012-01-10
申请人： Homare Sato
发明人： Homare Sato
IPC分类号： G11C5/06
CPC分类号： G11C11/408 , G06F12/0207 , G06F12/0223 , G06F12/08 , G11C5/02 , G11C5/04 , G11C8/12 , G11C11/4063 , H01L23/481 , H01L25/18 , H01L2224/16145
摘要： Such a device is disclosed that includes a first semiconductor chip including a plurality of first terminals, a plurality of second terminals, and a first circuit coupled between the first and second terminals and configured to control combinations of the first terminals to be electrically connected to the second terminals, and a second semiconductor chip including a plurality of third terminals coupled respectively to the second terminals, an internal circuit, and a second circuit coupled between the third terminals and the internal circuit and configured to activate the internal circuit when a combination of signals appearing at the third terminals indicates a chip selection.
摘要翻译：公开了一种这样的装置，其包括：第一半导体芯片，包括多个第一端子，多个第二端子，以及耦合在第一和第二端子之间的第一电路，并且被配置为控制第一端子的组合以电连接到第二端子和包括分别耦合到第二端子的多个第三端子的第二半导体芯片，内部电路和耦合在第三端子和内部电路之间的第二电路，并且被配置为当信号的组合时激活内部电路出现在第三个终端表示芯片选择。

10. 发明申请

US20120195090A1 SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER 有权
标题翻译：半导体器件，其中包括堆叠在一起的其他一些
公开(公告)号：US20120195090A1
公开(公告)日：2012-08-02
申请号：US13358448
申请日：2012-01-25
申请人： Junichi HAYASHI , Homare Sato
发明人： Junichi HAYASHI , Homare Sato
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C5/02
摘要： Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to the first chip. The second output circuit supplies the first command signal to the second chip. The third output circuit supplies a second command signal to the first and second chips.
摘要翻译：公开了这样的装置，其包括彼此堆叠的第一和第二芯片，以及控制堆叠在第一和第二芯片上的第一和第二芯片的第三芯片，并且包括第一，第二和第三输出电路。第一输出电路向第一芯片提供第一命令信号。第二输出电路将第一命令信号提供给第二芯片。第三输出电路向第一和第二芯片提供第二命令信号。

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