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1. 发明授权

US08331122B2 Semiconductor device and information processing system including the same 有权
标题翻译：半导体装置和信息处理系统也包括在内
公开(公告)号：US08331122B2
公开(公告)日：2012-12-11
申请号：US12923749
申请日：2010-10-06
申请人： Homare Sato , Junichi Hayashi
发明人： Homare Sato , Junichi Hayashi
IPC分类号： G11C5/02 , H01L23/12
CPC分类号： G11C11/408 , G11C7/1066 , H01L2224/13 , H01L2224/16145 , H01L2224/16225
摘要： A semiconductor device includes plural core chips and an interface chip that controls the plural core chips. Each of the plural core chips includes a layer address generating circuit that generates a second chip address by incrementing a value of a first chip address and a layer address comparing circuit that compares a third chip address supplied from the interface chip and the second chip address, and activates a chip selection signal when the third chip address and the second chip address are matched with each other. When a non-used chip signal is in an inactivated state, the layer address generating circuit supplies the second chip address to another core chip, and when the non-used chip signal is in an activated state, the layer address generating circuit supplies the first chip address to another core chip without a change.
摘要翻译：半导体器件包括多个核心芯片和控制多个芯片的接口芯片。多个核心芯片中的每一个包括通过增加第一芯片地址的值产生第二芯片地址的层地址产生电路和比较从接口芯片提供的第三芯片地址和第二芯片地址的层地址比较电路，并且当第三芯片地址和第二芯片地址彼此匹配时激活芯片选择信号。当未使用的芯片信号处于非激活状态时，层地址产生电路将第二芯片地址提供给另一核心芯片，并且当未使用的芯片信号处于激活状态时，层地址产生电路提供第一芯片芯片地址到另一个核心芯片没有变化。

2. 发明授权

US09378775B2 Semiconductor device including plural chips stacked to each other 有权
标题翻译：包括彼此堆叠的多个芯片的半导体装置
公开(公告)号：US09378775B2
公开(公告)日：2016-06-28
申请号：US13358448
申请日：2012-01-25
申请人： Junichi Hayashi , Homare Sato
发明人： Junichi Hayashi , Homare Sato
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C5/06 , G11C5/02
CPC分类号： G11C5/063 , G11C5/02
摘要： Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to the first chip. The second output circuit supplies the first command signal to the second chip. The third output circuit supplies a second command signal to the first and second chips.
摘要翻译：公开了这样的装置，其包括彼此堆叠的第一和第二芯片，以及控制堆叠在第一和第二芯片上的第一和第二芯片的第三芯片，并且包括第一，第二和第三输出电路。第一输出电路向第一芯片提供第一命令信号。第二输出电路将第一命令信号提供给第二芯片。第三输出电路向第一和第二芯片提供第二命令信号。

3. 发明申请

US20110087835A1 Semiconductor memory device and data processing system 有权
标题翻译：半导体存储器件和数据处理系统
公开(公告)号：US20110087835A1
公开(公告)日：2011-04-14
申请号：US12923790
申请日：2010-10-07
申请人： Homare Sato , Junichi Hayashi
发明人： Homare Sato , Junichi Hayashi
IPC分类号： G06F12/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/4072 , G11C11/4076 , G11C16/20 , G11C2211/4061
摘要： To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation.
摘要翻译：包括预先给出彼此不同的芯片信息片段的多个核心芯片。第一刷新命令被分成具有彼此不同定时的多个第二刷新命令，并且对于其中第二刷新命令的计数值和芯片信息的至少一部分匹配的核心芯片执行刷新操作彼此。利用这种配置，即使当第二刷新命令被共同地提供给多个核心芯片时，也可以移动每个核心芯片中的刷新操作的定时。因此，可以减少刷新时的峰值电流。

4. 发明授权

US08885430B2 Semiconductor memory device and data processing system 有权
标题翻译：半导体存储器件和数据处理系统
公开(公告)号：US08885430B2
公开(公告)日：2014-11-11
申请号：US12923790
申请日：2010-10-07
申请人： Homare Sato , Junichi Hayashi
发明人： Homare Sato , Junichi Hayashi
IPC分类号： G11C7/00 , G06F12/00 , G11C11/4072 , G11C11/406 , G11C16/20 , G11C11/4076
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/4072 , G11C11/4076 , G11C16/20 , G11C2211/4061
摘要： To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation.
摘要翻译：包括预先给出彼此不同的芯片信息片段的多个核心芯片。第一刷新命令被分成具有彼此不同定时的多个第二刷新命令，并且对于其中第二刷新命令的计数值和芯片信息的至少一部分匹配的核心芯片执行刷新操作彼此。利用这种配置，即使当第二刷新命令被共同地提供给多个核心芯片时，也可以移动每个核心芯片中的刷新操作的定时。因此，可以减少刷新时的峰值电流。

5. 发明申请

US20110085397A1 Semiconductor device and information processing system including the same 有权
标题翻译：半导体装置和信息处理系统也包括在内
公开(公告)号：US20110085397A1
公开(公告)日：2011-04-14
申请号：US12923749
申请日：2010-10-06
申请人： Homare Sato , Junichi Hayashi
发明人： Homare Sato , Junichi Hayashi
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/408 , G11C7/1066 , H01L2224/13 , H01L2224/16145 , H01L2224/16225
摘要： A semiconductor device includes plural core chips and an interface chip that controls the plural core chips. Each of the plural core chips includes a layer address generating circuit that generates a second chip address by incrementing a value of a first chip address and a layer address comparing circuit that compares a third chip address supplied from the interface chip and the second chip address, and activates a chip selection signal when the third chip address and the second chip address are matched with each other. When a non-used chip signal is in an inactivated state, the layer address generating circuit supplies the second chip address to another core chip, and when the non-used chip signal is in an activated state, the layer address generating circuit supplies the first chip address to another core chip without a change.
摘要翻译：半导体器件包括多个核心芯片和控制多个芯片的接口芯片。多个核心芯片中的每一个包括通过增加第一芯片地址的值产生第二芯片地址的层地址产生电路和比较从接口芯片提供的第三芯片地址和第二芯片地址的层地址比较电路，并且当第三芯片地址和第二芯片地址彼此匹配时激活芯片选择信号。当未使用的芯片信号处于非激活状态时，层地址产生电路将第二芯片地址提供给另一核心芯片，并且当未使用的芯片信号处于激活状态时，层地址产生电路提供第一芯片芯片地址到另一个核心芯片没有变化。

6. 发明授权

US09077914B2 Image processing apparatus and control method thereof printing image data having M tones under infrared light 有权
标题翻译：图像处理装置及其控制方法在红外光下打印具有M个色调的图像数据
公开(公告)号：US09077914B2
公开(公告)日：2015-07-07
申请号：US13277064
申请日：2011-10-19
申请人： Koji Harada , Junichi Hayashi , Masanori Yokoi
发明人： Koji Harada , Junichi Hayashi , Masanori Yokoi
IPC分类号： H04N1/40 , H04N1/32
CPC分类号： H04N1/32309 , H04N2201/0082 , H04N2201/327 , H04N2201/3271
摘要： This invention can generate printed matter on which a multi-valued discrimination image of three values or more cannot be visually confirmed under ordinary light but can be visually confirmed via an infrared camera under infrared light. To this end, a holding unit holds items of color information C1, C2, and C3 each indicating usage amounts of printing materials of three types, used by a printing apparatus, which have a color difference under visible light not more than a pre-set threshold, and which have different infrared light ray absorption rates. When a latent image generating unit generates infrared light ray latent image data of three tones, a discrimination image data generating unit decides one color information item Ci (1≦i≦3) held by the holding unit, and outputs the decided Ci to an output unit which outputs the received pixel values to the printing apparatus.
摘要翻译：本发明可以生成在普通的光下不能视觉确认三值以上的多值辨别图像的印刷物，但是可以通过红外线照相机在红外光下目视确认。为此，保持单元保存颜色信息C1，C2和C3的项目，每个颜色信息C1，C2和C3分别表示打印设备使用的三种类型的打印材料的使用量，其在不超过预设的可见光下具有色差阈值，并具有不同的红外光线吸收率。当潜像产生单元产生三个音调的红外光线潜像数据时，鉴别图像数据生成单元确定由保持单元保持的一个颜色信息项目Ci（1＆nlE; i＆nlE; 3），并将所确定的Ci输出到输出将所接收的像素值输出到打印装置的单元。

7. 发明申请

US20140247684A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140247684A1
公开(公告)日：2014-09-04
申请号：US14279386
申请日：2014-05-16
申请人： Junichi Hayashi
发明人： Junichi Hayashi
IPC分类号： G11C11/4076 , G11C11/408
CPC分类号： G11C11/4076 , G11C5/025 , G11C5/063 , G11C11/408 , G11C11/4082 , G11C11/4087 , H01L2224/16145
摘要： A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips.
摘要翻译：半导体器件包括：接口芯片，包括读定时控制电路，其响应于来自外部的命令信号和时钟信号输出与时钟信号同步的多个读控制信号，并且具有不同的时间核心芯片包括堆叠在接口芯片上的多个内部电路，并且每个都与读取的控制信号同步地执行由命令信号指示的操作。根据本发明，不需要控制核心芯片的等待时间，从而将时钟信号提供给核心芯片。

8. 发明授权

US08250661B2 Image processing apparatus, information processing apparatus, and methods thereof 有权
标题翻译：图像处理装置，信息处理装置及其方法
公开(公告)号：US08250661B2
公开(公告)日：2012-08-21
申请号：US11615128
申请日：2006-12-22
申请人： Junichi Hayashi
发明人： Junichi Hayashi
IPC分类号： G06F21/00 , G06F12/14 , G06Q20/00 , G06F7/04
CPC分类号： G06F21/10 , G06F21/6209 , H04L9/0844 , H04L2209/603 , H04N1/00204 , H04N1/32101 , H04N1/4486 , H04N2201/001 , H04N2201/3246
摘要： Upon applying a DRM protection process to an image which is generated by an image processing apparatus, which doesn't have any communication means that allows direct communications with a PC, without any alteration, encryption of the image in the apparatus and that of the image in the PC as an internal process of the DRM are required, resulting in poor efficiency. The apparatus executes a part of the DRM protection process for the image, and outputs the encrypted image. The PC receives the image which has undergone the part of the DRM protection process, executes the remaining part of the DRM protection process, and outputs the image which has undergone the DRM protection process. In this case, the PC transmits use condition of the input image to a license server, receives signed use condition from the server, and combines the signed use condition with the input encrypted image.
摘要翻译：在对由图像处理装置生成的图像应用DRM保护处理的情况下，不进行与PC直接通信的任何通信手段，而不进行任何改变，图像在图像中的加密和图像的加密在PC中作为DRM的内部过程是必需的，导致效率差。该装置执行图像的DRM保护处理的一部分，并输出加密图像。 PC接收经过DRM保护处理的部分的图像，执行DRM保护处理的剩余部分，并输出已经经过DRM保护处理的图像。在这种情况下，PC将输入图像的使用条件发送到许可证服务器，从服务器接收签名使用条件，并将签名的使用条件与输入的加密图像组合。

9. 发明申请

US20120127493A1 INFORMATION GENERATION APPARATUS, INFORMATION GENERATION METHOD, IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD 失效
标题翻译：信息生成装置，信息生成方法，图像处理装置和图像处理方法
公开(公告)号：US20120127493A1
公开(公告)日：2012-05-24
申请号：US13284719
申请日：2011-10-28
申请人： Masanori Yokoi , Junichi Hayashi , Koji Harada
发明人： Masanori Yokoi , Junichi Hayashi , Koji Harada
IPC分类号： G06K15/02 , G06K9/00
CPC分类号： H04N1/0087 , G06K15/189 , G06K15/4095 , H04N1/32309 , H04N1/6033 , H04N1/605 , H04N1/6072 , H04N2201/0082 , H04N2201/327 , H04N2201/3271
摘要： For a selected pixel value, amounts of color material used of respective color materials used to print a background region, and those of respective color materials used to print a latent image region are calculated. The calculated amounts of color material used are stored in a memory in association with the selected pixel value. Amounts of color material used corresponding to respective pixel values of a pixel value group are read out from the memory, and are output to a printing apparatus.
摘要翻译：对于所选择的像素值，计算用于打印背景区域的各个彩色材料使用的颜色材料的量以及用于打印潜像区域的各种颜色材料的颜色材料的量。所计算的颜色材料的量与所选择的像素值相关联地存储在存储器中。从存储器中读出与像素值组的各个像素值对应使用的颜色材料量，并将其输出到打印装置。

10. 发明申请

US20120127492A1 IMAGE PROCESSING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：图像处理装置及其控制方法
公开(公告)号：US20120127492A1
公开(公告)日：2012-05-24
申请号：US13277064
申请日：2011-10-19
申请人： Koji Harada , Junichi Hayashi , Masanori Yokoi
发明人： Koji Harada , Junichi Hayashi , Masanori Yokoi
IPC分类号： H04N1/60
CPC分类号： H04N1/32309 , H04N2201/0082 , H04N2201/327 , H04N2201/3271
摘要： This invention can generate printed matter on which a multi-valued discrimination image of three values or more cannot be visually confirmed under ordinary light but can be visually confirmed via an infrared camera under infrared light. To this end, a holding unit holds items of color information C1, C2, and C3 each indicating usage amounts of printing materials of three types, used by a printing apparatus, which have a color difference under visible light not more than a pre-set threshold, and which have different infrared light ray absorption rates. When a latent image generating unit generates infrared light ray latent image data of three tones, a discrimination image data generating unit decides one color information item Ci (1≦i≦3) held by the holding unit, and outputs the decided Ci to an output unit which outputs the received pixel values to the printing apparatus.
摘要翻译：本发明可以生成在普通的光下不能视觉确认三值以上的多值辨别图像的印刷物，但是可以通过红外线照相机在红外光下目视确认。为此，保持单元保存颜色信息C1，C2和C3的项目，每个颜色信息C1，C2和C3分别表示打印设备使用的三种类型的打印材料的使用量，其在不超过预设的可见光下具有色差阈值，并具有不同的红外光线吸收率。当潜像产生单元产生三个音调的红外光线潜像数据时，鉴别图像数据生成单元确定由保持单元保持的一个颜色信息项目Ci（1＆nlE; i＆nlE; 3），并将所确定的Ci输出到输出将所接收的像素值输出到打印装置的单元。

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