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1. 发明授权

US07589364B2 Electrically rewritable non-volatile memory element and method of manufacturing the same 有权
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US07589364B2
公开(公告)日：2009-09-15
申请号：US11264129
申请日：2005-11-02
申请人： Isamu Asano , Natsuki Sato , Tyler A. Lowrey , Guy C. Wicker , Wolodymyr Czubatyj , Stephen J. Hudgens
发明人： Isamu Asano , Natsuki Sato , Tyler A. Lowrey , Guy C. Wicker , Wolodymyr Czubatyj , Stephen J. Hudgens
IPC分类号： H01L31/112
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148
摘要： A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first through-hole 11, recording layer 15 containing phase change material provided in the second through-hole 12, a top electrode 16 provided on the second interlayer insulation layer 12, and a thin-film insulation layer 14 formed between the bottom electrode 13 and the recording layer 15. In accordance with this invention, the diameter D1 of a bottom electrode 13 buried in a first through-hole 11a is smaller than the diameter D2 of a second through-hole 12a, thereby decreasing the thermal capacity of the bottom electrode 13. Therefore, when a pore 14a is formed by dielectric breakdown in a thin-film insulation layer 14 and the vicinity is used as a heating region, the amount of heat escaping to the bottom electrode 13 is decreased, resulting in higher heating efficiency.
摘要翻译：非易失性存储元件包括具有第一通孔11a的第一层间绝缘层11，形成在第一层间绝缘层11上的第二通孔12a的第二层间绝缘层12，第一通孔11，设置在第二通孔12中的包含相变材料的记录层15，设置在第二层间绝缘层12上的顶部电极16和形成在底部电极13和记录层15.根据本发明，埋在第一通孔11a中的底部电极13的直径D1小于第二通孔12a的直径D2，从而降低底部电极的热容量因此，当通过薄膜绝缘层14中的电介质击穿形成孔14a并且将其附近用作加热区域时，向底部电极逸出的热量 13降低，导致更高的加热效率。

2. 发明授权

US07692272B2 Electrically rewritable non-volatile memory element and method of manufacturing the same 有权
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US07692272B2
公开(公告)日：2010-04-06
申请号：US11334504
申请日：2006-01-19
申请人： Isamu Asano , Natsuki Sato , Wolodymyr Czubatyj , Jeffrey P. Fournier
发明人： Isamu Asano , Natsuki Sato , Wolodymyr Czubatyj , Jeffrey P. Fournier
IPC分类号： H01L31/0264
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1625
摘要： A non-volatile memory element comprises a bottom electrode 12; a top electrode 15; and a recording layer 13 containing phase change material and a block layer 14 that can block phase change of the recording layer 13, provided between the bottom electrode 12 and the top electrode 15. The block layer 14 is constituted of material having an electrical resistance that is higher than that of material constituting the recording layer 13. The block layer 14 suppresses the radiation of heat towards the top electrode 15 and greatly limits the phase change region when a write current is applied. The result is a high heating efficiency. The top electrode 15 itself can be used to constitute a bit line, or a separate bit line can be provided.
摘要翻译：非易失性存储元件包括底部电极12; 顶部电极15; 以及包含相变材料的记录层13和可以阻挡设置在底部电极12和顶部电极15之间的记录层13的相变的阻挡层14.阻挡层14由具有电阻的材料构成，比构成记录层13的材料高。阻挡层14抑制向顶部电极15的热辐射，并且在施加写入电流时极大地限制相变区域。结果是高的加热效率。顶部电极15本身可以用于构成位线，或者可以提供单独的位线。

3. 发明申请

US20070096074A1 Electrically rewritable non-volatile memory element and method of manufacturing the same 有权
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US20070096074A1
公开(公告)日：2007-05-03
申请号：US11264129
申请日：2005-11-02
申请人： Isamu Asano , Natsuki Sato , Tyler Lowrey , Guy Wicker , Wolodymyr Czubatyj , Stephen Hudgens
发明人： Isamu Asano , Natsuki Sato , Tyler Lowrey , Guy Wicker , Wolodymyr Czubatyj , Stephen Hudgens
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148
摘要： A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first through-hole 11, recording layer 15 containing phase change material provided in the second through-hole 12, a top electrode 16 provided on the second interlayer insulation layer 12, and a thin-film insulation layer 14 formed between the bottom electrode 13 and the recording layer 15. In accordance with this invention, the diameter D1 of a bottom electrode 13 buried in a first through-hole 11a is smaller than the diameter D2 of a second through-hole 12a, thereby decreasing the thermal capacity of the bottom electrode 13. Therefore, when a pore 14a is formed by dielectric breakdown in a thin-film insulation layer 14 and the vicinity is used as a heating region, the amount of heat escaping to the bottom electrode 13 is decreased, resulting in higher heating efficiency.
摘要翻译：非易失性存储元件包括具有第一通孔11a的第一层间绝缘层11，具有形成在第一层间绝缘层11上的第二通孔12a的第二层间绝缘层12，在第一通孔11中，设置在第二通孔12中的包含相变材料的记录层15，设置在第二层间绝缘层12上的顶部电极16和形成在第二通孔12的底部电极之间的薄膜绝缘层14 13和记录层15。根据本发明，埋在第一通孔11a中的底部电极13的直径D 1小于第二通孔12a的直径D 2，从而降低底部电极13的热容量。因此，当通过薄膜绝缘层14中的电介质击穿形成孔14a并且将其附近用作加热区域时，逸出到底部电极13的热量减少，导致更高的加热效率。

4. 发明申请

US20070164267A1 Electrically rewritable non-volatile memory element and method of manufacturing the same 有权
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US20070164267A1
公开(公告)日：2007-07-19
申请号：US11334504
申请日：2006-01-19
申请人： Isamu Asano , Natsuki Sato , Wolodymyr Czubatyj , Jeffrey Fournier
发明人： Isamu Asano , Natsuki Sato , Wolodymyr Czubatyj , Jeffrey Fournier
IPC分类号： H01L29/06 , H01L21/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1625
摘要： A non-volatile memory element comprises a bottom electrode 12; a top electrode 15; and a recording layer 13 containing phase change material and a block layer 14 that can block phase change of the recording layer 13, provided between the bottom electrode 12 and the top electrode 15. The block layer 14 is constituted of material having an electrical resistance that is higher than that of material constituting the recording layer 13. The block layer 14 suppresses the radiation of heat towards the top electrode 15 and greatly limits the phase change region when a write current is applied. The result is a high heating efficiency. The top electrode 15 itself can be used to constitute a bit line, or a separate bit line can be provided.
摘要翻译：非易失性存储元件包括底部电极12; 顶部电极15; 以及包含相变材料的记录层13和可以阻挡设置在底部电极12和顶部电极15之间的记录层13的相变的阻挡层14.阻挡层14由具有电阻的材料构成，比构成记录层13的材料高。阻挡层14抑制向顶部电极15的热辐射，并且在施加写入电流时极大地限制相变区域。结果是高的加热效率。顶部电极15本身可以用于构成位线，或者可以提供单独的位线。

5. 发明申请

US20080042119A1 Multi-layered chalcogenide and related devices having enhanced operational characteristics 审中-公开
标题翻译：具有增强的操作特性的多层硫族化物和相关装置
公开(公告)号：US20080042119A1
公开(公告)日：2008-02-21
申请号：US11821246
申请日：2007-06-22
申请人： Regino Sandoval , Wolodymyr Czubatyj , Tyler Lowrey , Isamu Asano
发明人： Regino Sandoval , Wolodymyr Czubatyj , Tyler Lowrey , Isamu Asano
IPC分类号： H01L47/00
CPC分类号： H01L45/1246 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625
摘要： A multi-layer chalcogenide, memory or switching device. The device includes an active region disposed between a first terminal and a second terminal. The active region includes a first layer and a second layer, where one of the layers is a heterogeneous layer that includes an operational component and a promoter component. The other layer may be a homogeneous or heterogeneous layer. In exemplary embodiments, the operational component is a chalcogenide or phase change material and the promoter component is an insulating or dielectric material. Inclusion of the promoter component provides beneficial performance characteristics such as a reduction in reset current or minimization of formation requirements.
摘要翻译：多层硫族化物，记忆体或开关装置。该装置包括设置在第一端子和第二端子之间的有源区域。有源区包括第一层和第二层，其中一层是包含可操作组分和促进剂组分的异质层。另一层可以是均质或非均质层。在示例性实施方案中，操作组分是硫族化物或相变材料，并且促进剂组分是绝缘或介电材料。包含启动子组分提供了有益的性能特征，例如复位电流的降低或形成要求的最小化。

6. 发明授权

US07723715B2 Memory device and method of making same 有权
标题翻译：存储器件及其制作方法
公开(公告)号：US07723715B2
公开(公告)日：2010-05-25
申请号：US11602923
申请日：2006-11-21
申请人： Wolodymyr Czubatyj , Tyler Lowrey , Isamu Asano
发明人： Wolodymyr Czubatyj , Tyler Lowrey , Isamu Asano
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/122 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a first area of electrical communication with the phase-change material. A second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, and the second area being laterally spacedly disposed from the first area. Additionally, the radial memory device includes a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer having an opening therethrough, the phase-change material being disposed in the opening, wherein the phase-change material is disposed at least partially above the second electrode. Further, a method of making a memory device is disclosed.
摘要翻译：径向存储器件包括相变材料，与相变材料电连通的第一电极，第一电极具有与相变材料电连通的第一区域。与所述相变材料电连通的第二电极，所述第二电极具有与所述相变材料电连通的第二区域，并且所述第二区域与所述第一区域横向间隔设置。此外，径向存储器件包括设置在第一电极和第二电极之间的电介质层，电介质层具有穿过其中的开口，相变材料设置在开口中，其中相变材料至少部分地设置在第二电极之上。此外，公开了一种制造存储器件的方法。

7. 发明申请

US20070063181A1 Memory device and method of making same 有权
标题翻译：存储器件及其制作方法
公开(公告)号：US20070063181A1
公开(公告)日：2007-03-22
申请号：US11602923
申请日：2006-11-21
申请人： Wolodymyr Czubatyj , Tyler Lowrey , Isamu Asano
发明人： Wolodymyr Czubatyj , Tyler Lowrey , Isamu Asano
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/122 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A radial memory device includes a phase-change material, a first electrode in electrical communication with the phase-change material, the first electrode having a first area of electrical communication with the phase-change material. A second electrode in electrical communication with the phase-change material, the second electrode having a second area of electrical communication with the phase-change material, and the second area being laterally spacedly disposed from the first area. Additionally, the radial memory device includes a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer having an opening therethrough, the phase-change material being disposed in the opening, wherein the phase-change material is disposed at least partially above the second electrode. Further, a method of making a memory device is disclosed.
摘要翻译：径向存储器件包括相变材料，与相变材料电连通的第一电极，第一电极具有与相变材料电连通的第一区域。与所述相变材料电连通的第二电极，所述第二电极具有与所述相变材料电连通的第二区域，并且所述第二区域与所述第一区域横向间隔设置。此外，径向存储器件包括设置在第一电极和第二电极之间的电介质层，电介质层具有穿过其中的开口，相变材料设置在开口中，其中相变材料至少部分地设置在第二电极之上。此外，公开了一种制造存储器件的方法。

8. 发明授权

US07671356B2 Electrically rewritable non-volatile memory element and method of manufacturing the same 有权
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US07671356B2
公开(公告)日：2010-03-02
申请号：US11265275
申请日：2005-11-03
申请人： Isamu Asano , Tyler A. Lowrey
发明人： Isamu Asano , Tyler A. Lowrey
IPC分类号： H01L47/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C2213/52 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A non-volatile memory element comprising a bottom electrode 12, a top electrode 17 provided on the bottom electrode 12, and a recording layer 18 containing phase change material connected between the bottom electrode 12 and the top electrode 17. In accordance with this invention, the top electrode 17 is in contact with a growth initiation surface 18a of the recording layer 17. This structure can be obtained by forming the top electrode 17 before the recording layer 18, resulting in a three-dimensional structure. This decreases heat dissipation to the bit line without increasing the thickness of the recording layer 18.
摘要翻译：包括底部电极12，设置在底部电极12上的顶部电极17和包含连接在底部电极12和顶部电极17之间的相变材料的记录层18的非易失性存储元件。根据本发明，顶部电极17与记录层17的生长起始表面18a接触。这种结构可以通过在记录层18之前形成顶部电极17而获得，从而形成三维结构。这降低了对位线的散热，而不增加记录层18的厚度。

9. 发明授权

US07541607B2 Electrically rewritable non-volatile memory element and method of manufacturing the same 有权
标题翻译：电可重写非易失性存储元件及其制造方法
公开(公告)号：US07541607B2
公开(公告)日：2009-06-02
申请号：US11264091
申请日：2005-11-02
申请人： Isamu Asano , Tyler A. Lowrey
发明人： Isamu Asano , Tyler A. Lowrey
IPC分类号： H01L29/02
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A non-volatile memory element includes a bottom electrode 12, a bit line 14 provided on the bottom electrode 12, and a recording layer 15 containing phase change material connected between the bottom electrode 12 and the bit line 14. In accordance with this invention, the bit line 14 is in contact with a growth initiation surface 15a of the recording layer 15. This structure can be obtained by forming the bit line 14 before the recording layer 15, resulting in a three-dimensional structure. This decreases the area of contact between the recording layer 15 and the bit line 14, decreasing heat dissipation to the bit line 14 without increasing the thickness of the recording layer 15. With this three-dimensional structure, moreover, there is no top electrode between the bit line 14 and the recording layer 15, keeping down the complexity of the fabrication process.
摘要翻译：非易失性存储元件包括底部电极12，设置在底部电极12上的位线14和包含连接在底部电极12和位线14之间的相变材料的记录层15.根据本发明，位线14与记录层15的生长起始表面15a接触。这种结构可以通过在记录层15之前形成位线14而获得，从而形成三维结构。这降低了记录层15和位线14之间的接触面积，从而减小了对位线14的散热，而不增加记录层15的厚度。此外，通过这种三维结构，在三维结构之间不存在顶部电极位线14和记录层15，从而降低制造工艺的复杂性。

10. 发明授权

US08129709B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08129709B2
公开(公告)日：2012-03-06
申请号：US12618302
申请日：2009-11-13
申请人： Akiyoshi Seko , Yukio Fuji , Natsuki Sato , Isamu Asano
发明人： Akiyoshi Seko , Yukio Fuji , Natsuki Sato , Isamu Asano
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A nonvolatile memory device (21) is provided with a semiconductor substrate, a plurality of active regions (3) formed on the semiconductor substrate and extending in a band, a plurality of select active elements (23) formed in the active regions (3) and having a first impurity diffusion region and a second impurity diffusion region, a plurality of first electrodes (13) electrically connected to the first impurity diffusion region, a variable resistance layer (12) electrically connected to the first electrodes (13), and a plurality of second electrodes electrically connected to the variable resistance layer (12). Among the plurality of first electrodes (13) and the plurality of second electrodes, an array direction of at least one pair of the first electrodes (13) and the second electrodes that are electrically connected to the same variable resistance layer (12), and a direction of extension of the activation regions (3) are not parallel.
摘要翻译：非易失性存储器件（21）设置有半导体衬底，形成在半导体衬底上并在带中延伸的多个有源区（3），形成在有源区（3）中的多个选择有源元件（23）并具有第一杂质扩散区域和第二杂质扩散区域，与第一杂质扩散区域电连接的多个第一电极（13），与第一电极（13）电连接的可变电阻层（12），以及电连接到可变电阻层（12）的多个第二电极。在多个第一电极（13）和多个第二电极中，电连接到同一可变电阻层（12）的至少一对第一电极（13）和第二电极的排列方向，以及激活区域（3）的延伸方向不平行。

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