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1. 发明授权

US09589608B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09589608B2
公开(公告)日：2017-03-07
申请号：US12730859
申请日：2010-03-24
申请人： Akiyoshi Seko
发明人： Akiyoshi Seko
IPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C13/00
CPC分类号： G11C7/12 , G11C7/02 , G11C7/18 , G11C13/0026 , G11C13/004
摘要： In a semiconductor memory device storing a resistance difference as information, a long time is taken so as to charge and/or discharge a selected cell by an equalizer circuit, which results in a difficulty of a high speed operation. A selection circuit puts, in a selected state, at least three bit lines which includes a selected bit line connected to a selected memory cell together with unselected bit lines adjacent to the selected bit line on both sides of the selected bit line. The selected and the unselected bit lines are coupled to sense amplifiers through an equalizer circuit. The equalizer circuit puts both the selected and the unselected bit lines into charging states and thereafter puts only the selected bit line into a discharging state to perform a sensing operation. On the other hand, the unselected bit lines are continuously kept at the charging states during the sensing operation. This makes it possible to perform the sensing operation at a high speed with a rare malfunction.
摘要翻译：在存储电阻差作为信息的半导体存储器件中，采取长时间以便通过均衡器电路对所选择的单元进行充电和/或放电，这导致高速操作的困难。选择电路以选定的状态放置至少三条位线，其包括连接到所选择的存储器单元的选定位线以及与选定位线两侧所选位线相邻的未选定位线。所选择的和未选择的位线通过均衡器电路耦合到读出放大器。均衡器电路将所选择的和未选择的位线都放入充电状态，然后仅将所选位线置于放电状态以执行感测操作。另一方面，在感测操作期间，未选择的位线被连续地保持在充电状态。这使得可以以罕见的故障高速执行感测操作。

2. 发明申请

US20100246302A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100246302A1
公开(公告)日：2010-09-30
申请号：US12730859
申请日：2010-03-24
申请人： Akiyoshi SEKO
发明人： Akiyoshi SEKO
IPC分类号： G11C7/06 , G11C7/14
CPC分类号： G11C7/12 , G11C7/02 , G11C7/18 , G11C13/0026 , G11C13/004
摘要： In a semiconductor memory device storing a resistance difference as information, a long time is taken so as to charge and/or discharge a selected cell by an equalizer circuit, which results in a difficulty of a high speed operation. A selection circuit puts, in a selected state, at least three bit lines which includes a selected bit line connected to a selected memory cell together with unselected bit lines adjacent to the selected bit line on both sides of the selected bit line. The selected and the unselected bit lines are coupled to sense amplifiers through an equalizer circuit. The equalizer circuit puts both the selected and the unselected bit lines into charging states and thereafter puts only the selected bit line into a discharging state to perform a sensing operation. On the other hand, the unselected bit lines are continuously kept at the charging states during the sensing operation. This makes it possible to perform the sensing operation at a high speed with a rare malfunction.
摘要翻译：在存储电阻差作为信息的半导体存储器件中，采取长时间以便通过均衡器电路对所选择的单元进行充电和/或放电，这导致高速操作的困难。选择电路以选定的状态放置至少三条位线，其包括连接到所选择的存储器单元的选定位线以及与选定位线两侧所选位线相邻的未选定位线。所选择的和未选择的位线通过均衡器电路耦合到读出放大器。均衡器电路将所选择的和未选择的位线都放入充电状态，然后仅将所选位线置于放电状态以执行感测操作。另一方面，在感测操作期间，未选择的位线被连续地保持在充电状态。这使得可以以罕见的故障高速执行感测操作。

3. 发明授权

US07780001B2 File wrapper for wrapping 失效
标题翻译：用于包装的文件包装器
公开(公告)号：US07780001B2
公开(公告)日：2010-08-24
申请号：US11192463
申请日：2005-07-26
申请人： Akiyoshi Seko
发明人： Akiyoshi Seko
IPC分类号： B65D85/57
CPC分类号： G11B33/0422 , G11B33/0494
摘要： A file wrapper for wrapping is provided. The file wrapper for wrapping comprises a file wrapper for wrapping comprising: a the cutting body, which comprises a unit piece of a covering paper and a backing paper of integral constitution that is bent to form a bag shape, sealing pieces provided to the covering paper and the backing paper, at the opening portion of the bag shape for inserting commodities, respectively, and side sticking pieces provided to the both sides portion of the covering paper. The one sealing piece is provided with a stopper of commodities after inserting them, and the other sealing piece is provided with the connecting piece inserted in the notch hole of the stopper and engaged thereto.
摘要翻译：提供了一个用于包装的文件包装。用于包装的文件包装件包括用于包装的文件包装件，包括：切割体，其包括被覆的纸的单位片和被弯曲形成袋形状的整体构造的背纸，设置在覆盖纸上的密封片以及背纸，分别在用于插入商品的袋形的开口部分和设置在覆盖纸的两侧部分的侧贴片。一个密封件在插入之后设置有商品塞子，另一个密封件设置有插入塞子的切口孔中并与其接合的连接片。

4. 发明申请

US20100195415A1 Semiconductor memory device and reading method therefor 审中-公开
标题翻译：半导体存储器件及其读取方法
公开(公告)号：US20100195415A1
公开(公告)日：2010-08-05
申请号：US12656484
申请日：2010-02-01
申请人： Akiyoshi Seko
发明人： Akiyoshi Seko
IPC分类号： G11C5/14 , G11C7/02 , G11C7/00
CPC分类号： G11C7/02 , G11C5/145 , G11C5/147 , G11C7/12 , G11C11/1673 , G11C11/1693
摘要： A memory device is configured such that, in a read access: a first switch and a second switch are turned on in a pre-charge period before a memory cell is accessed so that charges of a bit line charge voltage generating circuit are distributed to a bit line and a reference bit line, to thereby charge the bit line and the reference bit line to an initial voltage. After the charge, a selected memory cell is connected to the bit line, the reference bit line is connected to a reference voltage generating circuit, and a voltage differential type sense amplifier amplifies a difference voltage between a voltage of the bit line decreased by discharge of the selected memory cell and a voltage of the reference bit line generated by the reference voltage generating circuit, to thereby read out memory cell data.
摘要翻译：存储器件被配置为使得在读取访问中：第一开关和第二开关在存储单元被访问之前的预充电周期中被接通，使得位线充电电压产生电路的电荷被分配到位线和参考位线，从而将位线和参考位线充电到初始电压。在充电之后，选择的存储单元连接到位线，参考位线连接到参考电压产生电路，并且电压差分型读出放大器放大位线减小的电压之间的差值电压所选择的存储单元和由参考电压产生电路产生的参考位线的电压，从而读出存储单元数据。

5. 发明授权

US08787068B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08787068B2
公开(公告)日：2014-07-22
申请号：US13440633
申请日：2012-04-05
申请人： Akiyoshi Seko , Tatsuya Matano
发明人： Akiyoshi Seko , Tatsuya Matano
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C2013/0071 , G11C2213/74 , G11C2213/79
摘要： A semiconductor device includes first and second interconnects, a variable resistance element that may assume a first resistance value or a second resistance value in response to the current flowing therein, first and second transistors connected between the first and second interconnects in series with each other on both sides of the variable resistance element, and a power supply circuit unit that delivers the power supply to a control electrode of the first transistor. The power supply circuit unit supplies the power of a first power supply when the variable resistance element is to make transition to the first resistance value and the power supply circuit unit supplies the power of a second power supply when the variable resistance element is to make transition to the second resistance value, thereby allowing transitioning of the resistance values of the variable resistance element.
摘要翻译：半导体器件包括第一和第二互连，可变电阻元件，其响应于其中流过的电流而呈现第一电阻值或第二电阻值，第一和第二晶体管彼此串联连接在第一和第二互连之间可变电阻元件的两侧，以及将电源输送到第一晶体管的控制电极的电源电路单元。当可变电阻元件要转变到第一电阻值时，电源电路单元提供第一电源的电力，并且当可变电阻元件要转变时，电源电路单元提供第二电源的电力到第二电阻值，从而允许可变电阻元件的电阻值的转变。

6. 发明申请

US20110214025A1 Control method of non-volatile semiconductor device 有权
标题翻译：非易失性半导体器件的控制方法
公开(公告)号：US20110214025A1
公开(公告)日：2011-09-01
申请号：US12929939
申请日：2011-02-25
申请人： Akiyoshi Seko
发明人： Akiyoshi Seko
IPC分类号： G06F11/00
CPC分类号： G11C13/0004 , G11C13/0023 , G11C13/0061 , G11C13/0064 , G11C13/0069
摘要： Disclosed is a control method of a non-volatile semiconductor device including cells, wherein a stress for rewriting information is applied to each of the cells, and each cell has a first time period as a period of time until a characteristic of the cell is stabilized to expectation value information after the stress for rewriting information is applied, a plurality of first sequences, in each of which writing is performed to a plurality of the cells continuously in time series, and a plurality of second sequences, in each of which verification of a plurality of the cells is performed continuously in time series, after the writing performed continuous in time series. When repeating, continuously in time series, a plurality of sets, each of the sets comprising a plurality of the first sequences and a plurality of the second sequences, a period of time from completion of application of the stress to each of the cells in the first sequence until start of the verification in the second sequence for the each of the cells subjected to the stress application, is arranged for each of all of the sets, wherein the period of time is the first time period or more.
摘要翻译：公开了一种包括单元的非易失性半导体器件的控制方法，其中用于重写信息的应力施加到每个单元，并且每个单元具有作为单元的特性稳定的一段时间的第一时间段在应用用于重写信息的应力之后的期望值信息中，在时间序列中连续地对多个单元执行写入的多个第一序列和多个第二序列，其中每个序列的验证在写入以时间序列连续进行之后，以时间序列连续地执行多个单元。当以时间序列连续重复多个集合时，每个集合包括多个第一序列和多个第二序列，从完成应用应用到每个小区中的每个小区的时间段对于经受应力施加的每个单元的第二序列中的开始验证的第一序列被布置用于所有集合中的每一个，其中所述时间段是第一时间段或更长时间。

7. 发明申请

US20100123114A1 NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20100123114A1
公开(公告)日：2010-05-20
申请号：US12618302
申请日：2009-11-13
申请人： Akiyoshi SEKO , Yukio FUJI , Natsuki SATO , Isamu ASANO
发明人： Akiyoshi SEKO , Yukio FUJI , Natsuki SATO , Isamu ASANO
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/148 , H01L45/1666
摘要： A nonvolatile memory device (21) is provided with a semiconductor substrate, a plurality of active regions (3) formed on the semiconductor substrate and extending in a band, a plurality of select active elements (23) formed in the active regions (3) and having a first impurity diffusion region and a second impurity diffusion region, a plurality of first electrodes (13) electrically connected to the first impurity diffusion region, a variable resistance layer (12) electrically connected to the first electrodes (13), and a plurality of second electrodes electrically connected to the variable resistance layer (12). Among the plurality of first electrodes (13) and the plurality of second electrodes, an array direction of at least one pair of the first electrodes (13) and the second electrodes that are electrically connected to the same variable resistance layer (12), and a direction of extension of the activation regions (3) are not parallel.
摘要翻译：非易失性存储器件（21）设置有半导体衬底，形成在半导体衬底上并在带中延伸的多个有源区（3），形成在有源区（3）中的多个选择有源元件（23）并具有第一杂质扩散区和第二杂质扩散区，与第一杂质扩散区电连接的多个第一电极（13），与第一电极（13）电连接的可变电阻层（12），以及电连接到可变电阻层（12）的多个第二电极。在多个第一电极（13）和多个第二电极中，电连接到同一可变电阻层（12）的至少一对第一电极（13）和第二电极的排列方向，以及激活区域（3）的延伸方向不平行。

8. 发明申请

US20090221146A1 Nonvolatile memory device and manufacturing method for the same 审中-公开
标题翻译：非易失存储器件及其制造方法相同
公开(公告)号：US20090221146A1
公开(公告)日：2009-09-03
申请号：US12379772
申请日：2009-02-27
申请人： Akiyoshi Seko , Natsuki Sato , Isamu Asano
发明人： Akiyoshi Seko , Natsuki Sato , Isamu Asano
IPC分类号： H01L21/306
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/128 , H01L45/144 , H01L45/1675
摘要： The object of the present invention is to provide a manufacturing method for a nonvolatile memory device including a variable resistance having a constricted shape. The nonvolatile memory device of the present invention has a storage section composed of two electrodes and a variable resistance sandwiched between the electrodes. The variable resistance is formed to a constricted shape between the electrodes.
摘要翻译：本发明的目的是提供一种包括具有收缩形状的可变电阻的非易失性存储装置的制造方法。本发明的非易失性存储器件具有由两个电极组成的存储部分和夹在电极之间的可变电阻。可变电阻形成为电极之间的缩小形状。

9. 发明申请

US20060108404A1 File wrapper for wrapping 失效
标题翻译：用于包装的文件包装器
公开(公告)号：US20060108404A1
公开(公告)日：2006-05-25
申请号：US11192463
申请日：2005-07-26
申请人： Akiyoshi Seko
发明人： Akiyoshi Seko
IPC分类号： B65D27/00 , B65D27/04 , B65D27/12 , B65D85/30
CPC分类号： G11B33/0422 , G11B33/0494
摘要： A file wrapper for wrapping is provided. The file wrapper for wrapping comprises a file wrapper for wrapping comprising: a die cutting body, which comprises a unit piece of a covering paper and a backing paper of integral constitution that is bent to form a bag shape, sealing pieces provided to the covering paper and the backing paper, at the opening portion of the bag shape for inserting commodities, respectively, and side sticking pieces provided to the both sides portion of the covering paper. The one sealing piece is provided with a stopper of commodities after inserting them, and the other sealing piece is provided with the connecting piece inserted in the notch hole of the stopper and engaged thereto.
摘要翻译：提供了一个用于包装的文件包装。用于包装的文件包装件包括用于包装的文件包装件，其包括：模切体，其包括被覆纸的单位片和被弯曲形成袋形的整体构造的背纸，设置在覆盖纸上的密封片以及背纸，分别在用于插入商品的袋形的开口部分和设置在覆盖纸的两侧部分的侧贴片。一个密封件在插入之后设置有商品塞子，另一个密封件设置有插入塞子的切口孔中并与其接合的连接片。

10. 发明申请

US20090104779A1 Method of producing phase change memory device 有权
标题翻译：相变存储器件的制造方法
公开(公告)号：US20090104779A1
公开(公告)日：2009-04-23
申请号：US12289002
申请日：2008-10-17
申请人： Akiyoshi Seko , Natsuki Sato , Isamu Asano
发明人： Akiyoshi Seko , Natsuki Sato , Isamu Asano
IPC分类号： H01L21/308 , H01L45/00
CPC分类号： H01L45/1233 , G11C13/0004 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/1273 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/16
摘要： An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller.
摘要翻译：需要减小下电极与可变电阻材料接触的区域，以降低可变电阻存储器件的功耗。本发明提供一种制造可变电阻存储元件的方法，由此可以使下电极形成得更小。将各向异性蚀刻工艺与各向同性蚀刻工艺相结合，能够使下部电极形成得更小。

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