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1. 发明授权

US4536663A Comparator circuit having full supply common mode input 失效
标题翻译：比较器电路具有全电源共模输入
公开(公告)号：US4536663A
公开(公告)日：1985-08-20
申请号：US510006
申请日：1983-07-01
申请人： Ira Miller , Robert C. Rumbaugh , John J. Price, Jr.
发明人： Ira Miller , Robert C. Rumbaugh , John J. Price, Jr.
IPC分类号： H03F3/45 , G01R19/00 , H03K5/08 , H03K5/24 , H03K3/02
CPC分类号： G01R19/0038 , H03K5/2418
摘要： The input voltage signals to a comparison circuit may vary between levels substantial equal to the first and second supply voltages (e.g. typically 5 volts and ground). A first transistor circuit is coupled to a current mirror circuit and to an output node for supplying a mirrorable current to the current mirror circuit which in turn reduces the voltage at the output node when the first input voltage approaches the upper supply voltage, and supplies a current to the output to increase the voltage thereat when the second input approaches the upper supply voltage. A second transistor circuit is also coupled to the current mirror and to the output for supplying a mirrorable current to the current mirror means so as to reduce the voltage at the output when the second input voltage approaches ground, and supplies current to the output to increase the voltage thereat when the first input voltage approaches ground. The output node has coupled thereto a level shifting transistor and first and second follower transistors.
摘要翻译：到比较电路的输入电压信号可以在基本等于第一和第二电源电压（例如通常为5伏和接地）之间的电平之间变化。第一晶体管电路耦合到电流镜电路和输出节点，用于向电流镜电路提供可反映的电流，这反过来在第一输入电压接近上电源电压时降低输出节点处的电压，并且提供当第二输入接近上电源电压时，电流到输出以增加其电压。第二晶体管电路还耦合到电流镜和输出端，用于向电流镜装置提供可镜像电流，以便当第二输入电压接近时减小输出端的电压，并将电流提供给输出以增加当第一个输入电压接近时的电压。输出节点与电平移动晶体管和第一和第二跟随器晶体管耦合。

2. 发明授权

US4554468A Latching comparator with hysteresis 失效
标题翻译：滞后比较器
公开(公告)号：US4554468A
公开(公告)日：1985-11-19
申请号：US510044
申请日：1983-07-01
申请人： Robert C. Rumbaugh , Ira Miller
发明人： Robert C. Rumbaugh , Ira Miller
IPC分类号： H03K3/2897 , H03K5/24
CPC分类号： H03K3/2897
摘要： A self latching comparator circuit has upper and lower input offset voltages associated therewith to establish hysteresis in response to a differential input signal. The comparator circuit comprises a differential amplifier adapted to receive a differential input signal and first and second parallel current mirror circuits for producing upper and lower input offset voltages when each are respectively activated. Antisaturation means are provided for preventing the current mirror circuits from saturating. An output circuit is also provided which does not load the differential output and therefore provides for a well controlled hysteresis.
摘要翻译：自锁定比较器电路具有与其相关联的上部和下部输入偏移电压，以响应于差分输入信号建立滞后。比较器电路包括适于接收差分输入信号的差分放大器，以及当各自分别激活时产生上和下输入偏移电压的第一和第二并联电流镜电路。提供了抗饱和装置，用于防止电流镜电路饱和。还提供了一个输出电路，它不加载差分输出，因此提供良好控制的滞后。

3. 发明申请

US20150158282A1 METHOD FOR PRODUCING A JOINT 有权
标题翻译：生产接头的方法
公开(公告)号：US20150158282A1
公开(公告)日：2015-06-11
申请号：US12745828
申请日：2008-12-03
申请人： Xavier Morral , Francisco Turegano , Ira Miller , Christophe Henry
发明人： Xavier Morral , Francisco Turegano , Ira Miller , Christophe Henry
IPC分类号： B32B37/12 , B32B37/14 , C09J163/00
CPC分类号： B32B37/1207 , B21D39/021 , B29C44/18 , B32B5/20 , B32B37/1292 , B32B37/142 , B32B2038/0084 , B32B2605/00 , B60J5/0469 , B62D27/026 , C09J163/00 , F16B11/006
摘要： Means for joining two surfaces comprise providing a heat activated sealant (7) at the end of one of the surfaces and inserting the end into a C or U shaped cup in the end of the other surface and heating to cause the sealant (7) to flow and join the surfaces. Preferably the sealant (7) is foamable, the invention is particularly useful in the production of automobile hem flanges.
摘要翻译：用于接合两个表面的装置包括在一个表面的端部提供热活化的密封剂（7），并将端部插入到另一个表面的端部中的C形或U形的杯中并加热以使密封剂（7）流动并连接表面。优选地，密封剂（7）是可发泡的，本发明特别可用于制造汽车下摆法兰。

4. 发明申请

US20060158170A1 Clocked ramp apparatus for voltage regulator softstart and method for softstarting voltage regulators 有权
公开(公告)号：US20060158170A1
公开(公告)日：2006-07-20
申请号：US11038746
申请日：2005-01-18
申请人： Brett Thompsen , Ira Miller , Eduardo Velarde
发明人： Brett Thompsen , Ira Miller , Eduardo Velarde
IPC分类号： G05F1/40 , G05F1/618
CPC分类号： G05F1/468 , Y10S323/901
摘要： Methods and apparatus for softstarting a voltage regulation circuit. A circuit for generating an output voltage at an output thereof includes a capacitor having a first terminal configured to be coupled to a reference potential and having a second terminal coupled to the output, and a switchable current source coupled to the capacitor for intermittently charging the capacitor until the output voltage is reached.

5. 发明授权

US4792899A Microprocessor support integrated circuit 失效
标题翻译：微处理器支持集成电路
公开(公告)号：US4792899A
公开(公告)日：1988-12-20
申请号：US1
申请日：1987-01-02
申请人： Ira Miller
发明人： Ira Miller
IPC分类号： G06F3/023 , G05F3/20 , G10L5/00 , G04B1/00
CPC分类号： G06F3/023
摘要： A single chip integrated circuit is partitioned to support a microprocessor chip for providing the logic interface between a keyboard peripherally connected to a host computer. The support circuit includes in a single integrated chip a voltage regulator, a serial to parallel converter, a multiple output current source, an oscillator, a DC to DC converter, an audio driver and LED drivers. The voltage regulator produces a plurality of regulated output voltages utilized to operate the microprocessor and the internal circuitry of the support circuit and is comprised of a band gap regulator and output of which is coupled to an external resistor for providing a reference current. The current source is coupled to the voltage regulator and provides a plurality of output currents ratioed with respect to the reference current. The serial to parallel converter converts serial digital data supplied from the microprocessor into parallel data for controlling the operation of the audio and LED driver circuits. The LED driver circuit converts currents supplied thereto from the current source to a higher magnitude sufficient for driving individual LEDs. The audio driver circuit provides a logarithmic output current thereat as controlled by said data.
摘要翻译：单芯片集成电路被分割以支持微处理器芯片，用于在外围连接到主计算机的键盘之间提供逻辑接口。支持电路在单个集成芯片中包括电压调节器，串并转换器，多输出电流源，振荡器，DC-DC转换器，音频驱动器和LED驱动器。电压调节器产生用于操作微处理器和支持电路的内部电路的多个调节输出电压，并且包括带隙调节器，其输出端耦合到用于提供参考电流的外部电阻器。电流源耦合到电压调节器并且提供与参考电流成比例的多个输出电流。串行到并行转换器将从微处理器提供的串行数字数据转换为并行数据，以控制音频和LED驱动器电路的操作。 LED驱动器电路将从电流源提供的电流转换为足以驱动各个LED的更高的量值。音频驱动器电路提供由所述数据控制的对数输出电流。

6. 发明授权

US4501974A Pulse stretching and level shifting circuit 失效
标题翻译：脉冲拉伸和电平移位电路
公开(公告)号：US4501974A
公开(公告)日：1985-02-26
申请号：US449035
申请日：1982-12-13
申请人： Ira Miller , Michael W. Null , Robert N. Dotson
发明人： Ira Miller , Michael W. Null , Robert N. Dotson
IPC分类号： H03K5/003 , H03K5/04 , H03K17/56 , H03K3/017
CPC分类号： H03K5/003 , H03K5/04
摘要： A pulse stretching integrated circuit includes an on-chip capacitor. A first transistor means including an input transistor and an emitter follower transistor supplies a charging current to the capacitor so as to charge it to a first voltage when an input signal pulse is in a first logical state. A differential transistor pair has a first input coupled to the emitter follower transistor and to the capacitor and has a second input coupled to a reference voltage for generating a first output when the capacitor voltage is less than the reference voltage and for generating a second output when the capacitive voltage is greater than the reference voltage. An additional transistor is coupled to the capacitor for discharging the capacitor when the input signal pulse is in a second logical state causing the voltage at the first input of the differential pair to fall below the reference voltage.
摘要翻译：脉冲拉伸集成电路包括片上电容器。包括输入晶体管和射极跟随器晶体管的第一晶体管装置向电容器提供充电电流，以便当输入信号脉冲处于第一逻辑状态时将其充电到第一电压。差分晶体管对具有耦合到射极跟随器晶体管和电容器的第一输入，并且具有耦合到参考电压的第二输入，用于当电容器电压小于参考电压时产生第一输出，并且当第电容电压大于参考电压。当输入信号脉冲处于第二逻辑状态时，附加晶体管耦合到电容器，用于对电容器进行放电，导致差分对的第一输入处的电压低于参考电压。

7. 发明申请

US20070273340A1 Buck-boost control logic for PWM regulator 有权
标题翻译：用于PWM调节器的降压 - 升压控制逻辑
公开(公告)号：US20070273340A1
公开(公告)日：2007-11-29
申请号：US11429613
申请日：2006-05-05
申请人： Ira Miller , Eduardo Velarde
发明人： Ira Miller , Eduardo Velarde
IPC分类号： G05F1/613
CPC分类号： H02M3/1582
摘要： A PWM regulator is operated either a buck mode or a boost mode depending on whether the input voltage is above or below the desired regulated output voltage. The technique uses two sawtooth ramps 180 degrees out of phase. Where the two ramps cross each other is a buck/boost transition level. An error voltage, corresponding to a required duty cycle to achieve a regulated voltage, is compared to the two ramps. The transition from one mode to the other occurs when the error voltage passes the buck/boost transition level of the two ramps. A logic circuit supplies PWM pulses to either buck switching transistors or the boost switching transistors in a power stage of the regulator, depending on the whether the error voltage is above or below the buck/boost transition level, to achieve the regulated voltage.
摘要翻译：根据输入电压是否高于或低于所需的稳压输出电压，PWM调节器工作在降压模式或升压模式。该技术使用两个相位相差180度的锯齿形斜坡。两个斜坡交叉的地方是降压/升压转换水平。将对应于实现调节电压的所需占空比的误差电压与两个斜坡进行比较。当错误电压通过两个斜坡的降压/升压转换电平时，从一种模式转换到另一种模式发生。逻辑电路根据误差电压是否高于或低于降压/升压转换电平，在调节器的功率级中降压开关晶体管或升压开关晶体管，从而实现调节电压。

8. 发明授权

US4647841A Low voltage, high precision current source 失效
标题翻译：低电压，高精度电流源
公开(公告)号：US4647841A
公开(公告)日：1987-03-03
申请号：US789605
申请日：1985-10-21
申请人： Ira Miller
发明人： Ira Miller
IPC分类号： G05F3/26 , G05F3/20
CPC分类号： G05F3/267
摘要： A precision current mirror circuit includes first and second transistors the bases of which are coupled together and whose emitters are coupled to ground. The collector of the first transistor is connected to a reference current source for sinking a reference current therefrom while the collector of the second transistor is connected to an output of the current error for sinking a current at the output that substantially mirrors the reference current. A differential amplifier is provided having its non-inverting and inverting inputs coupled to the collectors of the first and second transistors respectively and its output connected to the bases of the two transistors such that the voltage that is established at the output of the current mirror is forced onto the collector of the first transistor. With the two transistors being matched the respective collector-base voltages therefore track which eliminates "Early" voltage errors as well as affects of the lower output impedances of the two transistors.
摘要翻译：精密电流镜电路包括第一和第二晶体管，其基极耦合在一起并且其发射极耦合到地。第一晶体管的集电极连接到参考电流源，用于从其中吸收参考电流，而第二晶体管的集电极连接到电流误差的输出，用于吸收基本上反映参考电流的输出处的电流。提供了一种差分放大器，其非反相和反相输入端分别耦合到第一和第二晶体管的集电极，其输出端连接到两个晶体管的基极，使得在电流镜的输出处建立的电压为强制到第一晶体管的集电极上。在两个晶体管匹配时，相应的集电极 - 基极电压因此跟踪消除了“早期”电压误差以及两个晶体管的较低输出阻抗的影响。

9. 发明授权

US4533844A Peak storage amplifier 失效
标题翻译：峰值存储放大器
公开(公告)号：US4533844A
公开(公告)日：1985-08-06
申请号：US694895
申请日：1985-01-24
申请人： Ira Miller , Robert B. Davies
发明人： Ira Miller , Robert B. Davies
IPC分类号： G01R19/04 , G11C27/02 , H03F3/72 , H03F3/45
CPC分类号： H03F3/72 , G01R19/04 , G11C27/026
摘要： A peak storage amplifier for storing successive peaks of a waveform for a sufficient period of time to insure accurate data transmittal is provided. A differential amplifier is responsive to the waveform and drives a PNP transistor that provides an output. A capacitor stores the peaks of the output waveform as long as a clamp signal is received by a current source that inhibits the current source from sinking the output to ground. Since the PNP transistor is continually reversed biased and the base-collector capacitance is small, the storage capacitor's discharge due to the amplifiers inherent turn-off characteristics is minimized. A compensation capacitor coupled to the differential amplifier prevents the collapse of a Wilson mirror serving as a load to the differential amplifier.
摘要翻译：提供一种峰值存储放大器，用于在足够的时间段内存储波形的连续峰值以确保准确的数据传输。差分放大器响应波形并驱动提供输出的PNP晶体管。一个电容器存储输出波形的峰值，只要钳位信号被电流源接收，阻止电流源将输出端接地。由于PNP晶体管被连续反向偏置并且基极 - 集电极电容小，所以存储电容器由放大器固有的关断特性引起的放电最小化。耦合到差分放大器的补偿电容器防止作为负载的威尔逊反射镜的塌陷到差分放大器。

10. 发明授权

US4514651A ECL To TTL output stage 失效
标题翻译： ECL到TTL输出级
公开(公告)号：US4514651A
公开(公告)日：1985-04-30
申请号：US450415
申请日：1982-12-16
申请人： Ira Miller , Michael W. Null
发明人： Ira Miller , Michael W. Null
IPC分类号： H03K19/013 , H03K19/018 , H03K19/092 , H03K19/086 , H03K19/088
CPC分类号： H03K19/013 , H03K19/01806
摘要： In a circuit for converting signals having ECL logic levels to a signal having TTL logic levels, the level shift is accomplished using the base-emitter drops of the transistors employed to avoid the speed degradation that accompanies the use of resistors as level shifters. First and second complementary input ECL signals are applied to first and second transistors respectively. The first input signal results in rendering a drive transistor conductive which turns the source transistor means in a push-pull output stage off and the sink transistor in the output stage on. When the second input signal goes high, current is diverted so as to render the drive transistor nonconductive. Additional circuit means are provided for preventing the sink transistor from saturating and for preventing the input of the source transistor means from falling below a predetermined level. Circuit means are also provided for turning the source transistor means off quickly so as to improve the overall speed performance of the circuit.
摘要翻译：在用于将具有ECL逻辑电平的信号转换为具有TTL逻辑电平的信号的电路中，使用用于避免伴随使用电阻器作为电平移位器的速度劣化的晶体管的基极 - 发射极点来实现电平移位。第一和第二互补输入ECL信号分别施加到第一和第二晶体管。第一输入信号导致驱动晶体管导通，使源极晶体管装置在推挽输出级中断开，并且输出级中的漏极晶体管导通。当第二输入信号变为高电平时，电流被转向以使驱动晶体管不导通。提供了附加的电路装置，用于防止漏极晶体管饱和并且防止源极晶体管装置的输入降低到预定水平以下。还提供用于快速转动源晶体管装置的电路装置，以便提高电路的整体速度性能。

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