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1. 发明申请

US20020177253A1 Process for making a high voltage NPN Bipolar device with improved AC performance 审中-公开
标题翻译：制造具有改进的交流性能的高压NPN双极器件的工艺
公开(公告)号：US20020177253A1
公开(公告)日：2002-11-28
申请号：US09866319
申请日：2001-05-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Vidhya Ramachandran
IPC分类号： H01L021/00
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A method of improving the speed of a heterojunction bipolar device without negatively impacting ruggedness of the device is provided. This method includes the steps of providing a structure that includes at least a bipolar device region, the bipolar device region comprising at least a collector region formed over a sub-collector region; and forming an n-type dopant region within the collector region, wherein the n-type dopant region has a vertical width that is less than about 2000 null and a peak concentration that is greater than a peak concentration of the collector region. The present invention also provides a method of fabricating a heterojunction bipolar transistor device as well as the device itself which can be used in various applications including as a component for a mobile phone, a component of a personal digital assistant and other like applications wherein speed and ruggedness are required.
摘要翻译：提供了一种提高异质结双极器件的速度而不会不利地影响器件耐用性的方法。该方法包括提供包括至少双极器件区域的结构的步骤，所述双极器件区域至少包括形成在子集电极区域上的集电极区域; 以及在所述集电极区域内形成n型掺杂剂区域，其中所述n型掺杂剂区域具有小于约的垂直宽度和大于所述集电极区域的峰值浓度的峰值浓度。本发明还提供了一种制造异质结双极晶体管器件的方法以及可用于各种应用的器件本身，包括用作移动电话的组件，个人数字助理的组件以及其它类似的应用，其中速度和需要坚固性。

2. 发明申请

US20030057458A1 Bipolar device having shallow junction raised extrinsic base and method for making the same 失效
标题翻译：具有浅结的双极器件提出外在基极及其制造方法
公开(公告)号：US20030057458A1
公开(公告)日：2003-03-27
申请号：US09962738
申请日：2001-09-25
申请人： International Business Machines Corporation
发明人： Gregory G. Freeman , Seshadri Subbanna , Basanth Jagannathan , Kathryn T. Schonenberg , Shwu-Jen Jeng , Kenneth J. Stein , Jeffrey B. Johnson
IPC分类号： H01L029/80 , H01L031/112
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing. The heterojunction bipolar transistor simultaneously improves three factors that affect the speed and performance of bipolar transistors: base width, base resistance, and base-collector capacitance.
摘要翻译：本文公开了一种凸起的外在基极，硅锗（SiGe）异质结双极晶体管（HBT）及其制造方法。异质结双极晶体管包括基板，形成在基板上的硅锗层，形成在基板上的集电极层，形成在硅锗层上的升高的非本征基极层和形成在硅锗层上的发射极层。硅锗层在发射极层和凸起的非本征基极层之间形成异质结。双极晶体管还包括形成在凸起的非本征基极层的一部分上的基极，在集电极层的一部分上形成的集电极，以及形成在发射极层的一部分上的发射极。因此，异质结双极晶体管包括自对准凸起的外在基极，最小结深度以及影响基底宽度的最小间隙缺陷，全部以最小的热处理形成。异质结双极晶体管同时改善了影响双极晶体管速度和性能的三个因素：基极宽度，基极电阻和基极集电极电容。

3. 发明申请

US20040099895A1 High performance vertical PNP transistor and method 有权
标题翻译：高性能垂直PNP晶体管及方法
公开(公告)号：US20040099895A1
公开(公告)日：2004-05-27
申请号：US10065837
申请日：2002-11-25
申请人： International Business Machines Corporation
发明人： Peter B. Gray , Jeffrey B. Johnson
IPC分类号： H01L027/108
CPC分类号： H01L27/0826 , H01L21/82285 , Y10S438/969
摘要： The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.
摘要翻译：本发明包括用于制造用于BiCMOS器件的高性能垂直NPN和PNP晶体管的方法和结果。所产生的高性能垂直PNP晶体管包括包括硅和锗的发射极区域，并且其PNP发射极与NPN晶体管的基极共享单层硅。该方法为CMOS和双极器件的常规制造工艺增加了两个附加的掩模步骤，因此代表了整个工艺流程的微小添加。所得到的结构显着增强了PNP器件的性能。

4. 发明申请

US20040082124A1 High performance varactor diodes 失效
标题翻译：高性能变容二极管
公开(公告)号：US20040082124A1
公开(公告)日：2004-04-29
申请号：US10728140
申请日：2003-12-04
申请人： International Business Machines Corporation
发明人： Douglas D. Coolbaugh , Stephen S. Furkay , Mohamed Youssef Hammad , Jeffrey B. Johnson
IPC分类号： H01L021/8234
CPC分类号： H01L29/93 , H01L27/0808 , Y10S438/979
摘要： A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.
摘要翻译：一种变容二极管，具有在衬底中包括第一导电类型的阱区的第一电极，包括设置在所述阱区中的第二导电类型邻接隔离区的第一多个扩散区的第二电极和第二多个扩散所述第一导电类型的区域从不邻近所述隔离区域的所述第一多个扩散区域的部分横向延伸并且具有大于所述第一多个扩散区域的掺杂剂浓度的掺杂剂浓度。变容二极管在约0V至3V之间的施加电压范围内具有至少约3.5的可调谐性，约0V至2V之间的施加电压范围内的电容值的近似线性变化，以及至少约100的Q 大约2GHz的电路工作频率。

5. 发明申请

US20040061183A1 MULTIPLE CHIP GUARD RINGS FOR INTEGRATED CIRCUIT AND CHIP GUARD RING INTERCONNECT 有权
标题翻译：用于集成电路和芯片保护环互连的多芯片保护环
公开(公告)号：US20040061183A1
公开(公告)日：2004-04-01
申请号：US10261819
申请日：2002-10-01
申请人： International Business Machines Corporation , Innovative Systems and Technologies Corp.
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Parker A. Robinson , Raminderpal Singh , Dennis Whittaker
IPC分类号： H01L029/76
CPC分类号： H01L23/585 , H01L21/765 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit having structure for isolating circuit sections having at least one differing characteristic. The structure includes a chip guard ring for each circuit section having the at least one differing characteristic. Providing multiple chip guard rings allows for isolation of circuit sections and prevention of ionic contamination, but without increased expense and size. In addition, it is practicable with any IC. The invention also may include an interconnect for electrical connectivity about a chip guard ring.
摘要翻译：一种具有用于隔离具有至少一个不同特性的电路部分的结构的集成电路。该结构包括具有至少一个不同特征的每个电路部分的芯片保护环。提供多个芯片保护环允许隔离电路部分和防止离子污染，但不增加成本和尺寸。此外，任何IC都可行。本发明还可以包括用于围绕芯片保护环的电连接的互连。

6. 发明申请

US20030046046A1 Tetrahedralization of non-conformal three-dimensional mixed element meshes 失效
标题翻译：非共形三维混合元素网格的四面体化
公开(公告)号：US20030046046A1
公开(公告)日：2003-03-06
申请号：US09942419
申请日：2001-08-30
申请人： International Business Machines Corporation
发明人： Stephen E. Fischer , Jeffrey B. Johnson , Ralph W. Young
IPC分类号： G06G007/48
CPC分类号： G06T17/20
摘要： Undesirable Steiner points in tetrahedralized meshes may be minimized by tetrahedralization processes that order element subdivision based on degree of freedom data for elements in the mesh and/or treat element degree of freedom as non-static during element subdivision. Applying look-ahead, breadth-first-search subdivision, and other strategic subdivision techniques further minimizes the need for Steiner points.
摘要翻译：在四面体化网格中的不希望的Steiner点可以通过四面体化处理来最小化，该四面体化过程基于网格元素的自由度数据和/或在元素细分期间将元素自由度视为非静态来排序元素细分。应用前瞻性，广度优先搜索细分和其他战略细分技术进一步降低了对Steiner点的需求。

7. 发明申请

US20010023949A1 SOI active pixel cell design with grounded body contact 审中-公开
标题翻译： SOI有源像素单元设计，具有接地体接触
公开(公告)号：US20010023949A1
公开(公告)日：2001-09-27
申请号：US09862817
申请日：2001-05-22
申请人： International Business Machines Corporation
发明人： Jeffrey B. Johnson , Hon-Sum P. Wong
IPC分类号： H01L027/148
CPC分类号： H01L27/14609 , H01L27/1463
摘要： A photosensitive device includes an array of active pixel sensor devices, each APS device being formed in an isolated cell of silicon. Each cell has an insulating barrier around it, and sits upon an insulating layer formed on an underlying substrate. A semiconductor connector making vertical contact between the pinning layer and the body of each APS device preferably replaces at least some portion of the insulating barrier adjacent to each cell. The semiconductor connector may be a single vertical connection for each cell or it may be an elongated strip connecting multiple APS devices. It may extend only to the underlying insulating layer or it may extend through the insulating layer to the substrate, with the substrate acting to interconnect and ground the pinning layer and the body of each APS device. The invention also includes the method of making the photosensitive device.
摘要翻译：感光装置包括有源像素传感器装置的阵列，每个APS装置形成在隔离的硅电池中。每个电池在其周围具有绝缘屏障，并且位于形成在下面的衬底上的绝缘层上。在每个APS装置的钉扎层和主体之间进行垂直接触的半导体连接器优选地替代与每个电池相邻的绝缘屏障的至少一部分。半导体连接器可以是每个单元的单个垂直连接，或者可以是连接多个APS器件的细长条。它可以仅延伸到下面的绝缘层，或者它可以延伸穿过绝缘层到衬底，其中衬底用于互连和接地每个APS器件的钉扎层和主体。本发明还包括制造感光装置的方法。

8. 发明申请

US20040032004A1 High performance varactor diodes 失效
公开(公告)号：US20040032004A1
公开(公告)日：2004-02-19
申请号：US10064754
申请日：2002-08-14
申请人： International Business Machines Corporation
发明人： Douglas D. Coolbaugh , Stephen S. Furkay , Mohamed Youssef Hammad , Jeffrey B. Johnson
IPC分类号： H01L029/00 , H01L021/8238
CPC分类号： H01L29/93 , H01L27/0808 , Y10S438/979
摘要： A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

9. 发明申请

US20030122128A1 Novel varactors for CMOS and BiCMOS technologies 有权
标题翻译：用于CMOS和BiCMOS技术的新型变容二极管
公开(公告)号：US20030122128A1
公开(公告)日：2003-07-03
申请号：US10323022
申请日：2002-12-18
申请人： International Business Machines Corporation
发明人： Douglas D. Coolbaugh , James S. Dunn , Michael D. Gordon , Mohamed Y. Hammad , Jeffrey B. Johnson , David C. Sheridan
IPC分类号： H01L029/04
CPC分类号： H01L27/0811 , H01L27/0808 , H01L29/93 , H01L29/94
摘要： Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.
摘要翻译：提供了具有高可调性和/或与之相关的高品质因素的变形反应器及其制造方法。公开的一种类型的变容二极管是准超突发的基极 - 集电极结变容二极管，其包括在子集电极区域顶部具有第一导电类型的集电极区域的基板，所述集电极区域中存在多个隔离区域; 位于至少一对隔离区之间的贯穿植入区; 所述SiGe层位于所述衬底的不包含直通注入区域的部分之上，所述SiGe层具有不同于所述第一导电类型的第二导电类型的非本征基区; 以及位于外部基极区域和子集电极区域之间的锑注入区域。所公开的另一种类型的变容二极管是MOS变容二极管，其至少包括多晶硅栅极区域和阱区域，其中多晶硅栅极区域和阱区域具有相反的极性。

10. 发明申请

US20020197807A1 Non-self-aligned SiGe heterojunction bipolar transistor 审中-公开
标题翻译：非自对准SiGe异质结双极晶体管
公开(公告)号：US20020197807A1
公开(公告)日：2002-12-26
申请号：US09885792
申请日：2001-06-20
申请人： International Business Machines Corporation
发明人： Basanth Jagannathan , Shwu-Jen Jeng , Jeffrey B. Johnson , Robb A. Johnson , Louis D. Lanzerotti , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L021/331 , H01L021/8222
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/7378
摘要： A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.
摘要翻译：用于制造非自对准异质结双极晶体管的方法包括：在发射极堆叠中与多晶硅对准的PFET源极/漏极注入形成非本征基极区域，但不直接对准在该叠层中限定的发射极开口。这通过使发射器基座宽于发射器开口来实现。这有利地消除了非本征基区和发射极开口之间的对准的依赖性，从而导致更少的工艺步骤，减少的热循环和改进的速度。

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