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1. 发明公开

EP0724214A3 Distributed completion control in a microprocessor 失效
标题翻译：在微处理器分布式终止控制
公开(公告)号：EP0724214A3
公开(公告)日：1997-06-18
申请号：EP95480195.7
申请日：1995-12-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Olson, Christopher Hans , Potter, Terence Matthew , Vaden, Michael Thomas
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3857
摘要： The distributed completion mechanism maintains complex control dependence relations between instructions in a superscalar processor without the cycle time burden associated with large sequential queue structures. There are global busses, but none of them are cycle limiting (in general, they are almost latch-to-latch paths). The cost of this completion control mechanism is a large number of tag bits associated with each instruction stage, however, in light of shrinking lithography this cost is small and takes advantage of the strengths of newer technologies.

2. 发明公开

EP0874308A3 Store instruction forwarding technique with increased forwarding probability 失效
标题翻译：交通运输技术用于存储命令的推广概率较高
公开(公告)号：EP0874308A3
公开(公告)日：2001-01-24
申请号：EP98303037.0
申请日：1998-04-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Olson, Christopher Hans , Brooks, Jeffrey Scott
IPC分类号： G06F9/38
CPC分类号： G06F9/3826
摘要： Provided are a system and method for forwarding a first instruction in a processor. The processor comprises an execution unit and provides a plurality of instructions. The first instruction depends upon execution of a second instruction but does not otherwise require execution by the execution unit. The method first searches for the second instruction and then forwards the first instruction via the second instruction. One embodiment of the method and system forwards a store instruction in a processor. The store instruction has a source address. The processor provides a plurality of instructions. The method searches for a floating point instruction that is provided before the store instruction. The floating point instruction has a target address. The method then determines if the source address is equal to the target address. The method forwards the store instruction through the floating point instruction if the source address is equal to the target address.

3. 发明公开

EP0547835A3 An electronic circuit for performing floating point arithmetic functions 失效
标题翻译：用于执行浮点算术功能的电子电路
公开(公告)号：EP0547835A3
公开(公告)日：1993-08-18
申请号：EP92311237.9
申请日：1992-12-09
申请人： International Business Machines Corporation
发明人： Chu, Tan V. , Karim, Faraydon Osmond , Olson, Christopher Hans
IPC分类号： G06F7/544
CPC分类号： G06F7/5443 , G06F7/483 , G06F2207/386 , G06F2207/3884
摘要： An electronic circuit is disclosed for performing the floating point arithmetic operation A * B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A * B+C while using a full adder of three-quarters normal size.

4. 发明授权

EP0874308B1 Store instruction forwarding technique with increased forwarding probability 失效
标题翻译：交通运输技术用于存储命令的推广概率较高
公开(公告)号：EP0874308B1
公开(公告)日：2003-07-16
申请号：EP98303037.0
申请日：1998-04-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Olson, Christopher Hans , Brooks, Jeffrey Scott
IPC分类号： G06F9/38
CPC分类号： G06F9/3826

5. 发明公开

EP0933696A2 Single cycle direct execution of serializing instructions 审中-公开
标题翻译： Direkte Einzel-Zyklus-Ausführungvon Serialisierungsbefehlen
公开(公告)号：EP0933696A2
公开(公告)日：1999-08-04
申请号：EP99300235.1
申请日：1999-01-14
申请人： International Business Machines Corporation
发明人： Olson, Christopher Hans , Brooks, Jeffrey Scott
IPC分类号： G06F9/38
CPC分类号： G06F9/30094 , G06F9/3836 , G06F9/3857
摘要： A method and system for providing direct execution of a serializing instruction in a processor (1) is disclosed. The processor (1) has the serializing instruction and a nonserializing instruction. The processor (1) includes execution logic (38, 40) having a pipeline for executing the nonserializing instruction. The processor (1) also includes logic separate (110) from the execution logic (38, 40) for executing the serializing instruction. The method and system include recognizing the serializing instruction, recognizing the nonserializing instruction, providing the nonserializing instruction to the execution logic (38, 40), and providing the serializing instruction to the separate logic (110). The serializing instruction is executed without providing the serializing instruction to the pipeline.
摘要翻译：公开了一种用于在处理器（1）中直接执行串行化指令的方法和系统。处理器（1）具有串行化指令和非串行化指令。处理器（1）包括具有用于执行非串行化指令的流水线的执行逻辑（38,40）。处理器（1）还包括用于执行串行化指令的与执行逻辑（38,40）分离的逻辑（110）。所述方法和系统包括识别串行化指令，识别非串行化指令，向执行逻辑（38,40）提供非序列化指令，以及向分离逻辑（110）提供串行化指令。执行串行化指令，而不向管道提供串行化指令。

6. 发明公开

EP0724213A3 A method and system for reducing dispatch latency in a processor 失效
标题翻译：用于降低处理器的命令分配的等待时间的方法和装置
公开(公告)号：EP0724213A3
公开(公告)日：1997-05-28
申请号：EP95480192.4
申请日：1995-12-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Elliot, Timothy Alan , Olson, Christopher Hans , Muhich, John Stephen , Potter, Terence Matthew
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/3853
摘要： A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache relating to the reordering of the instructions. The reordered instructions are then provided to the appropriate execution units based upon the predetermined format. With this system, a dispatch buffer is not required when sending the instructions to the cache.

7. 发明公开

EP0540285A3 Method and apparatus for floating point normalisation 失效
标题翻译：浮点正态化的方法和装置
公开(公告)号：EP0540285A3
公开(公告)日：1993-08-11
申请号：EP92309814.9
申请日：1992-10-27
申请人： International Business Machines Corporation
发明人： Karim, Faraydon Osman , Olson, Christopher Hans
IPC分类号： G06F5/01
CPC分类号： G06F5/012 , G06F5/015
摘要： A method and apparatus for performing normalisation of floating point numbers using a much smaller width register than would normally be required for the data operands which can be processed. As the registers are smaller, the number of circuits required to achieve the normalisation is reduced, resulting in a decrease in the chip area required to perform such operation. The normalisation circuitry was streamlined to efficiently operate on the more prevalent type of data being presented to the floating point unit. Data types and/or operations which statistically occur less frequently require multiple cycles of the normalisation function. It was found that for the more prevalent data types and/or operations, the width of the registers required was substantially less than the width required for the less frequent data types and/or operations. Instead of expanding the register width to accommodate these lesser occurrences, the data is broken into smaller portions and normalised using successive cycles of the normalisation circuitry. Thus, by sacrificing speed for the lesser occurring events, a significant savings was realised in the number of circuits required to implement normalisation. As the slower speed operations occur infrequently, the overall performance of the normalisation function is minimally impacted. Thus, considerable savings in integrated circuit real estate is achieved with minimal impact to the overall throughput of the system.

8. 发明公开

EP0747809A1 A method and system for processing multiple branch instructions that write to count and/or link registers 失效
标题翻译：方法和系统，用于计数执行多个写入和/或连接分支指令的寄存器
公开(公告)号：EP0747809A1
公开(公告)日：1996-12-11
申请号：EP96480078.3
申请日：1996-05-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Olson, Christopher Hans , Golla, Robert T.
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/30061 , G06F9/3842 , G06F9/3863
摘要： A system and method for processing count and link branch instructions that allows multiple branches to be outstanding at the same time without being limited to the number of rename registers allocated to the count and link registers. The method and system comprises an architected count register and an architected link register that are each connected to a look-ahead register. Information in the architected count or link register is copied into the look-ahead register when a branch instruction is encountered that will alter the contents of the count or link registers. Information in the look-ahead register is saved in a shadow register when an unresolved branch is encountered, and restored by the shadow register if the outcome of the unresolved branch is mispredicted.
摘要翻译：一种用于处理计数和链接分支指令所做的系统和方法允许多个分支时尚未在Sametime而不限于重命名分配给计数和链接寄存器的寄存器的数目。架构计数寄存器和方法和系统，包括以架构链接寄存器做的每一个连接到一个先行登记。当一个分支指令中遇到的计数或链接寄存器的thatwill旧内容的架构计数或链接寄存器信息被复制到先行登记。在先行登记信息被保存在一个影子寄存器当遇到一个悬而未决的分支，并通过影子寄存器恢复，如果未解决分支的结果被错误预测。

9. 发明公开

EP0724214A2 Distributed completion control in a microprocessor 失效
标题翻译： Verteilte Beendigungssteuerung在einem Mikroprozessor
公开(公告)号：EP0724214A2
公开(公告)日：1996-07-31
申请号：EP95480195.7
申请日：1995-12-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Olson, Christopher Hans , Potter, Terence Matthew , Vaden, Michael Thomas
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3857
摘要： The distributed completion mechanism maintains complex control dependence relations between instructions in a superscalar processor without the cycle time burden associated with large sequential queue structures. There are global busses, but none of them are cycle limiting (in general, they are almost latch-to-latch paths). The cost of this completion control mechanism is a large number of tag bits associated with each instruction stage, however, in light of shrinking lithography this cost is small and takes advantage of the strengths of newer technologies.
摘要翻译：分布式完成机制保持超标量处理器中的指令之间的复杂的控制依赖关系，而不需要与大的顺序队列结构相关联的周期时间负担。有全局总线，但是它们都不是周期限制（通常它们几乎是锁存到锁存器的路径）。这种完成控制机制的成本是与每个指令阶段相关联的大量标签位，然而，鉴于光刻的缩小，这一成本很小，并且利用了较新技术的优点。

10. 发明公开

EP0677806A1 Efficient floating point overflow and underflow detection system 失效
标题翻译： DetektionssystemfürGleitkomma-Über-und Unterlauf。
公开(公告)号：EP0677806A1
公开(公告)日：1995-10-18
申请号：EP95480035.5
申请日：1995-03-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Elliott, Timothy Alan , Olson, Christopher Hans , Palermo, Frank
IPC分类号： G06F7/48 , G06F7/02
CPC分类号： G06F7/483 , G06F7/4991
摘要： A processing system that determines whether an underflow or overflow condition has occurred concurrently with the determination of the floating point exponent result uses a group of latched constants which can be added to the intermediate exponent and the exponent adjust to determine out of range conditions for all cases. The appropriate one of these latched constants (exponent range check values; exp_range_chk) are added to the exp_int and exp_adjust to give a value that will vary based on whether the exp_result is out of range, or not. Different exp_range_chk values are used for underflow single precision, underflow double precision, overflow single precision and overflow double precision. The sum of these three values (exp_int, exp_adj, exp_range_chk) will yield a binary number having a most significant bit (MSB) that is dependent upon the exp_result value. More particularly, the MSB will be a logical 1 when an out of range condition has occurred and a logical 0 for normal in range exponent results.
摘要翻译：确定下溢或溢出条件是否与浮点指数结果的确定同时发生的处理系统使用一组可被添加到中间指数的锁存常数，并且指数调整以确定所有情况的超出范围条件。这些锁存常量（指数范围检查值; exp_range_chk）中适当的一个被添加到exp_int和exp_adjust中，以给出一个值，该值将根据exp_result是否超出范围而变化。不同的exp_range_chk值用于下溢单精度，下溢双精度，溢出单精度和溢出双精度。这三个值的总和（exp_int，exp_adj，exp_range_chk）将产生一个具有最高有效位（MSB）的二进制数，这取决于exp_result值。更特别地，当超出范围条件已经发生时，MSB将是逻辑1，并且对于正常的范围指数结果中的逻辑0。

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