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1. 发明公开

US20240267334A1 DYNAMIC LOAD BALANCING FOR MULTI-CORE COMPUTING ENVIRONMENTS 审中-公开
公开(公告)号：US20240267334A1
公开(公告)日：2024-08-08
申请号：US18621516
申请日：2024-03-29
申请人： Intel Corporation
发明人： Stephen Palermo , Bradley Chaddick , Gage Eads , Mrittika Ganguli , Abhishek Khade , Abhirupa Layek , Sarita Maini , Niall McDonnell , Rahul Shah , Shrikant Shah , William Burroughs , David Sonnier
IPC分类号： H04L47/125 , H04L47/62 , H04L47/625 , H04L47/6275
CPC分类号： H04L47/125 , H04L47/62 , H04L47/624 , H04L47/6255 , H04L47/6275
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

2. 发明公开

US20230231809A1 DYNAMIC LOAD BALANCING FOR MULTI-CORE COMPUTING ENVIRONMENTS 审中-公开
公开(公告)号：US20230231809A1
公开(公告)日：2023-07-20
申请号：US18154619
申请日：2023-01-13
申请人： Intel Corporation
发明人： Stephen Palermo , Bradley Chaddick , Gage Eads , Mrittika Ganguli , Abhishek Khade , Abhirupa Layek , Sarita Maini , Niall McDonnell , Rahul Shah , Shrikant Shah , William Burroughs , David Sonnier
IPC分类号： H04L47/125 , H04L47/62 , H04L47/625 , H04L47/6275
CPC分类号： H04L47/125 , H04L47/62 , H04L47/624 , H04L47/6255 , H04L47/6275
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

3. 发明授权

US10929323B2 Multi-core communication acceleration using hardware queue device 有权
公开(公告)号：US10929323B2
公开(公告)日：2021-02-23
申请号：US16601137
申请日：2019-10-14
申请人： Intel Corporation
发明人： Ren Wang , Yipeng Wang , Andrew Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
IPC分类号： G06F13/37 , G06F9/54 , G06F12/0868 , G06F12/0811 , G06F13/16 , G06F12/04 , G06F9/38
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

4. 发明申请

US20220286399A1 HARDWARE QUEUE SCHEDULING FOR MULTI-CORE COMPUTING ENVIRONMENTS 有权
公开(公告)号：US20220286399A1
公开(公告)日：2022-09-08
申请号：US17637416
申请日：2020-09-11
申请人： Intel Corporation
发明人： Niall McDonnell , Gage Eads , Mrittika Ganguli , Chetan Hiremath , John Mangan , Stephen Palermo , Bruce Richardson , Edwin Verplanke , Praveen Mosur , Bradley Chaddick , Abhishek Khade , Abhirupa Layek , Sarita Maini , Rahul Shah , Shrikant Shah , William Burroughs , David Sonnier
IPC分类号： H04L47/125 , H04L47/625 , H04L47/62 , H04L47/6275
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

5. 发明申请

US20200042479A1 MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE 审中-公开
公开(公告)号：US20200042479A1
公开(公告)日：2020-02-06
申请号：US16601137
申请日：2019-10-14
申请人： Intel Corporation
发明人： Ren Wang , Yipeng Wang , Andrew Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
IPC分类号： G06F13/37 , G06F12/0811 , G06F13/16 , G06F9/54 , G06F12/0868
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

6. 发明授权

US10216668B2 Technologies for a distributed hardware queue manager 有权
公开(公告)号：US10216668B2
公开(公告)日：2019-02-26
申请号：US15087154
申请日：2016-03-31
申请人： Intel Corporation
发明人： Ren Wang , Yipeng Wang , Jr-Shian Tsai , Andrew Herdrich , Tsung-Yuan Tai , Niall McDonnell , Stephen Van Doren , David Sonnier , Debra Bernstein , Hugh Wilkinson , Narender Vangati , Stephen Miller , Gage Eads , Andrew Cunningham , Jonathan Kenny , Bruce Richardson , William Burroughs , Joseph Hasting , An Yan , James Clee , Te Ma , Jerry Pirog , Jamison Whitesell
IPC分类号： G06F13/24 , G06F13/36 , G06F13/40 , G06F12/1027
摘要： Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

7. 发明授权

US11575607B2 Dynamic load balancing for multi-core computing environments 有权
公开(公告)号：US11575607B2
公开(公告)日：2023-02-07
申请号：US17018809
申请日：2020-09-11
申请人： Intel Corporation
发明人： Stephen Palermo , Bradley Chaddick , Gage Eads , Mrittika Ganguli , Abhishek Khade , Abhirupa Layek , Sarita Maini , Niall McDonnell , Rahul Shah , Shrikant Shah , William Burroughs , David Sonnier
IPC分类号： H04L47/125 , H04L47/62 , H04L47/625 , H04L47/6275
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

8. 发明申请

US20210075730A1 DYNAMIC LOAD BALANCING FOR MULTI-CORE COMPUTING ENVIRONMENTS 有权
公开(公告)号：US20210075730A1
公开(公告)日：2021-03-11
申请号：US17018809
申请日：2020-09-11
申请人： Intel Corporation
发明人： Stephen Palermo , Bradley Chaddick , Gage Eads , Mrittika Ganguli , Abhishek Khade , Abhirupa Layek , Sarita Maini , Niall McDonnell , Rahul Shah , Shrikant Shah , William Burroughs , David Sonnier
IPC分类号： H04L12/803 , H04L12/863
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

9. 发明授权

US09864633B2 Network processor having multicasting protocol 有权
公开(公告)号：US09864633B2
公开(公告)日：2018-01-09
申请号：US14810039
申请日：2015-07-27
申请人： Intel Corporation
发明人： Deepak Mital , Joseph A. Manzella , Ritchie J. Peachey , William Burroughs
IPC分类号： H04L12/28 , G06F9/48 , H04L12/18 , G06F13/10
CPC分类号： G06F9/4881 , G06F13/102 , H04L12/18 , H04L12/1886
摘要： An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.

10. 发明申请

US20150331718A1 NETWORK PROCESSOR HAVING MULTICASTING PROTOCOL 有权
标题翻译：具有多媒体协议的网络处理器
公开(公告)号：US20150331718A1
公开(公告)日：2015-11-19
申请号：US14810039
申请日：2015-07-27
申请人： Intel Corporation
发明人： Deepak Mital , Joseph A. Manzella , Ritchie J. Peachey , William Burroughs
IPC分类号： G06F9/48 , H04L12/18 , G06F13/10
CPC分类号： G06F9/4881 , G06F13/102 , H04L12/18 , H04L12/1886
摘要： An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.
摘要翻译：描述了被配置为将多个数据分组多播到一个或多个引擎的网络处理器。在一个或多个实现中，网络处理器包括被配置为解析多个任务的输入/输出适配器。所述输入/输出适配器包括被配置为基于所述多个任务的最大多播值来确定参考计数值的多播模块。输入/输出适配器还被配置为在多个任务的控制数据部分内设置参考计数递减值。引用计数减量值基于最大组播值。输入/输出适配器还被配置为在从发动机接收到指示时将参考计数值减小相应的参考计数减量值。

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